The evolution of signal integrity analysis is similar to
many electronic design tasks. First,
best practices were followed. Second, analysis tools were used to verify final designs. Then, to reduce design
re-spins, what-if analysis techniques were created to drive constraints that
could then be verified at the end of the design cycle.
Because of tight schedules and time to market pressure,
there is often little time to circle back at the end of the design cycle when a
problem is discovered during the verification phase. The pressure is on to make sure that analysis
done early will identify all potential problems. However, as sophistication in analysis tools
increases, the data used in what-if analysis must also increase in
sophistication to provide meaningful results during the early design
An example of how sophisticated analysis tools are becoming
can be seen in memory interface analysis.
Many simultaneous switching signals on a DDR data bus with a less than
ideal current return path can cause noise referred to as simultaneous switching
noise (SSN). To understand the effects
of SSN, special I/O (Power-aware IBIS 5.0) and interconnect models (coupled
signal, power, and ground) must be utilized by the analysis tools. The IBIS 5.0 models must come from the memory
controller or memory provider. However,
power-aware interconnect models are typically extracted from a completed
Design team challenge
This creates a challenge for design teams wanting to explore
various strategies for understanding the impact of SSN on their future
designs. Once a design is fully routed,
it may be too late to correct a problem and still meet a tight schedule. To address this problem, the Allegro Sigrity
SI Base and Options provides the ability to create example configurations quickly
and then analyze those configurations using a variety of analysis techniques –
from first order to detailed 3D extraction and simulation.
The following video provides an example of how the Allegro
Sigrity SI Base lets you start with nothing and within minutes create sample
designs that can be used for early analysis.
As the video suggests, design teams using Allegro can benefit
from this early analysis by taking the working sample configurations and
copying the module into a design under development. The result will be a memory interface
pre-validated to be DDR compliant from a power-aware perspective.
If you have any feedback on the value of integrated design
and analysis technology, please let us know.
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