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What's Good About FSP’s Schematic Generation? 16.6 Has Many New Enhancements!

Comments(0)Filed under: Design Entry HDL, Librarians, FPGA: PCB, Schematic, FPGA, FPGA-PCB Co-Design, FPGA System Planner, Library, design, component browser, symbol, FPGAs, Grzenia, Allegro 16.6, 16.6, CadenceThe 16.6 release of Allegro FPGA System Planner (FSP) has MANY new enhancements in the area of schematic generation.

Some of the highlights:
  • Rules file can be added via the Component Browser as Real Interfaces
  • FPGAs can be linked to corporate symbols/footprints
  • Virtual Interfaces can be converted to Real Interfaces
  • FSP generated symbols can be customized as split symbols
  • Pin directions for generated symbols can be customized
  • Page borders, ports, etc. can be selected via the Component Browser
  • Part placement options


Some aspects of the above features were available in the 16.5 release as well.


Read on for more details…



Rules file added via the Component Browser as Real Interfaces
A rules file (LRF) that is placed into a design from the Library Explorer Interface Rules tab can be converted to a Real Interface. This RMB menu pick will open the Component Browser and allow you to pick the real part from the corporate library. The referenced rules file for the converted part will continue to be the rules file placed from Library Explorer. If FSP can automatically find the mapping file, that file name will be shown in the Mapping File field. If you want to use a different mapping file you can browse to a different one. You can also define the mapping from scratch by clicking on the “Define Mapping” button in the bottom left:




FPGAs can be linked to corporate symbols/footprints
An FPGA placed from FSP’s Library Explorer can also be linked to your corporate FPGA symbols. RMB on the FPGA and select “Link to Schematic Symbol…”. This will open Component Browser to allow selection of the FPGA from the corporate library. Update Instance Footprint… option (above “Link to Schematic Symbol…”) only updates the FPGA footprint from a dra file. It does not result in schgen using the schematic symbols from the corporate library:




Virtual Interfaces can be converted to Real Interfaces
Virtual Interfaced (VIs) can also be converted to Real Interfaces (this is not new in 16.6). But, when converting a VI to a Real Interface, FSP will create a rules file from the VI. You can enter a new name for the rules file or browse for the rules file, but FSP will overwrite any existing rules file (it will create a backup). Entering just a name for the rules file will result in the rules file being saved at the top level of the FSP project. You have to select an existing mapping file (you can also define the mapping from scratch):




FSP generated symbols can be customized as split symbols
A few other tricks to consider when generating symbols. By default FPGA symbols are split by banks. This can result in huge power symbols as there can be hundreds of power pins in large FPGAs. To force FSP to create smaller symbols you can select Customize Symbol on the Symbol Setup form, RMB on the top header row, select “Auto Split Symbol Pins”, and enter a maximum value for the number of pins in a split (note that parts selected from Component Browser cannot be customized since the corporate symbols are used during schematic generation):




Pin directions for generated symbols can be customized
Another thing that can lead to better looking symbols and schematics is to change how FSP/Genview places the generated symbol’s pins on the periphery of the symbol. The default is to distribute NC, bank power, and global power pins around the edge of the symbol. By changing these settings you can get cleaner looking symbols. This is not new in 16.6. The template.tsg file (normally located in the $CDS_SITE/ cdssetup/concept/genview directory) also affects the quality of the generated symbols:



Shematic generation options
16.6 adds and moves a few options for schematic generation. “Skip Unused Symbol Splits” has been moved from the Placement tab to the top level of the schematic generation form. 16.5 uses InOut as the port type for all pins on the top-level hierarchical block. With 16.6 you can force FSP to use the signal’s directions for the port type. The downside is that if the signal direction changes, the top level hierarchical block has to be updated. Schgen can flatten any hierarchical blocks used for terminations and filters. Power symbols can be automatically added to the schematics. Click on the “…” to invoke Component Browser to pick the appropriate power symbol for each rail:




Page borders, ports, etc. can be selected via the Component Browser
“Display Net Name as Instance Pin Name” allows you to use existing corporate symbols, but the pin name on the symbol is replaced with the name of the connected net. “Skip Terminations and Decaps” will force schgen to ignore any discrete power filter, termination, and decoupling caps in the generated schematic. Flat schematics can also be generated. These are harder to manage in the context of a larger design, but some customers demand flat schematics. When picking the page border, Ctap, Input, Output, etc. symbols, clicking on the … opens Component Browser (in 16.5 this used to be a drop-down selection mechanism):




Part placement options
The placement tab adds further controls over the settings defined in the cref.dat file. The page margins are in addition to what’s specified in the cref.dat file’s lowerleft, upperright, and excludearea settings. Component to Component spacing can be used to force Schgen to leave more space between components so that the cross-referencer has enough space for the cross-reference data. The Page Border information file refers points FSP/schgen to the cref.dat file:

 

 

I look forward to all your feedback on these new features!

Jerry “GenPart” Grzenia

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