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What's Good About FSP’s Design Compare? Check Out 16.6!

Comments(1)Filed under: PCB Layout and routing, PCB design, SPB, Design Entry HDL, Allegro, FPGA: PCB, PCB Editor, FPGA, FPGA-PCB Co-Design, FPGA System Planner, FSP, PCB, Taray, layout, design, FPGAs, Grzenia, Allegro 16.6, 16.6, comparing constraints

The 16.6 Allegro FPGA System Planner (FSP) product has an extremely helpful Design Compare capability.

With design changes done in Allegro PCB Editor the FSP designer needs to verify and, if they agree, accept the PCB designer’s changes. The FSP Design Compare form compares two FSP designs and is similar, but not identical, to the one used in Allegro PCB Editor.

The Design Compare form

Design Compare is a stand-alone form – it does not require the master, or any other design, to be open in FSP.
Click on the Design Compare icon or use the File > Design Compare pull-down:


In the Design Compare form, select the PCB copy on the right and the master design on the left (the order does not make a difference, but it’s easier to track differences if the master design is on the left).

Click the Compare button.

The “Show Only Diff” button helps to focus in on the differences. This is a “sticky” button – click to turn it on, click to turn it off.

The green arrows between the two sides and the yellow arrows at the top perform identical functions.

“Merge All To Left” and “Merge All To Right” will sync the designs in one step:

The FSP version of Design Compare is a little different than the one used in Allegro PCB editor. For one, there is no cross-probing in FSP like there is in Allegro. Also, in Allegro, the sections (connectivity, placement/ref des, etc.) are shown as tabs because the differences are displayed as a flattened list, for the entire design. In FSP, the items are displayed hierarchically and are selected from a drop-down:


Placement differences between the PCB copy and the FSP master are shown textually and graphically:


Merge the changes

You can merge all of the PCB changes into the FSP master. Click the “Merge All To Left” button:


You may encounter situations where an attempt to merge one signal(s) forces the merge of other signals:


This could happen if there is a cyclic dependency in the net connectivity. For example, if net n1 has to be moved to pin B26 and B26 is currently connected to net n2, then n1 and n2 are dependent nets. In other words, they both have to be moved together.

Please share your experiences using the FSP Design Compare capability.

Jerry “GenPart” Grzenia


By printed circuit board manufacturers on October 25, 2013
Thanks a lot for sharing. Keep blogging

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