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What's Good About PCB SI and Vias? 16.6 Has Many New Enhancements!

Comments(2)Filed under: PCB Signal and power integrity, Allegro, via, SI, Signal Intregrity, PCB, SigXP UI, layer stacks, PCB SI, "PCB design", SI analysis and modeling, design, PCB Signal integrity, "PCB SI", Allegro PCB SI, Design Reuse, signal integrity, inset vias, Grzenia, Allegro 16.6, 16.6, Cadence

In the Allegro PCB SI 16.6 release, vias in SigXp have been enhanced to make it more efficient for design use. In addition, Allegro PCB Editor padstacks will be used to build the models.

Read on for more details …

Adding Vias

Adding a via is easier and faster than before. You no longer have to go through the Via Model Generator to create a model nor are you required to search the list of existing models that fit the need. The difference is that you are now adding a via rather than a via model. The via may not be pre-solved to a specific model.

The current way of adding a via in SigXp is still supported and unchanged. You can still add a via model on the canvas.

In order to add these “dynamic” vias in SigXp, a layerstack will have to be present in the topology. In a new topology this can be accomplished by using the Manage LayerStacks function to create or import a layerstack. When a topology is extracted from Allegro, the layerstack of that board is automatically imported in the topology.

A new via is added with two nodes (two connection points) on the canvas. When newly added, the two nodes are not tied to any specific layer as they will take on the properties of the connected node, so the label of those nodes will be Layer1 and Layer2:

If a trace is connected and is on a particular layer then the via node is assumed to be on that layer and will take its properties. In the case of a "floating trace" (a trace not on a layer stack layer), the via node will take its properties and still say LayerX (unchanged). Since we do not know what layer that is, we will assume the top or bottom most layer of the via structure:

The prior release (16.5) via toolbar button is a two-part button which lists all available via models on the right hand side pulldown:

Clicking on the left side of the button (the one with the via image) brings up the Add Element Browser. In 16.6, the left part of the Add Via button will add the new “dynamic” via with only two nodes. The pulldown remains unchanged to list the pre-solved via models.

Reuse of Via Models

You will want to reuse already solved via models in SigXp. To do that, the same technique used today is available. You can either select the right button of the Add Via toolbar button, which will list all existing via models available sorted by types, or RMB > Add Element can still be used to choose the desired via model.

When these via models are added to the canvas, the model is “locked” to the via and cannot be changed - this is the via model that will be used to simulate.

Via Parameters

The new (dynamic) via has the following parameters which are listed in the standard parameters spreadsheet. These parameters can be modified:

model    The via model associated with the via. A via which has no model yet will have UNMODELED as a model. Once solved, the name of the model will be used.
viaOutputFormat    The format with which the model was solved. If no model exists yet, the format is blank.
viaPadstack    The name of an available padstack. This parameter is a pulldown which lists the available padstack files on disk and in the library.
viaTopLayer    The top most layer of the via drill.
viaBottomLayer    The bottom most layer of the via drill.

For coupled vias the parameters will be a little different. It will show the via name with which it is coupled as well as the distance between them. Aside from that, it will look just like a single via.

Padstack Consumption

SigXp can now consume and optionally modify the same padstacks as Allegro PCB Editor. You can to import *.pad files and keep them as file if they are different than the library.

You can access the Via Padstack Manager through the menus using Setup > Manage Via Padstacks, or by right clicking in the SigXp canvas and selecting Manage Via Padstacks. Editing or creating a new padstack will use the same padstack editor available in Allegro. The padstack can be saved as an external file. If shapes are associated with the padstack, they will be stored in the same location. All information in the padstack relevant to the via is used to generate the model:


Via Modeling

When a new “dynamic” via is added to the topology, no model is associated with it. Only when you perform a simulation or manually solve the via will the field solver be called. In batch mode, the field solver uses the standard via modeling preferences that are currently found in PCB SI. These settings are available in SigXp and can be accessed through the menus using Analyze > Via Setup Preferences or by right clicking in the SigXp canvas and selecting Via Setup Preferences:

The via subckt section is built using the padstack information, the layerstack and the connected traces, as is done in Allegro PCB SI. The via model is stored in the working IML file.

Coupling Vias

With this feature, you can couple 2 single vias to form one single model. You can select 2 vias in the SigXp canvas and select Couple from the right mouse button menu:

When the Couple function is used, you will be required to specify a spacing between the vias:

This spacing is added to the parameters in the spreadsheet:

When you select a coupled via, all vias in the set will be selected:

You can decouple the vias by selecting Decouple from the right mouse button when one of the vias is selected:

Please share your experiences using these 16.6 features.

Jerry "GenPart" Grzenia


By benyamin on July 19, 2014
I need the simple datasheet (manual) for signal integrity in allegro(cadence). please help me?

By Jerry GenPart on July 24, 2014
Hi Benyamin,
Here's a very good landing page for the Sigrity products: www.cadence.com/.../default.aspx
Jerry G.

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