will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST). login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Blogs > PCB Design > what s good about the spb 16 6 release exciting features to improve design productivity
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the PCB Design blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

What's Good About the SPB 16.6 Release? Exciting Features To Improve Design Productivity!


The SPB 16.6 Release is available! You can download it from the Cadence Software downloads site.

Here are just a few press announcements on the 16.6 release –

New Allegro 16.6 Release Accelerates Timing Closure on High-Speed PCB Interfaces by 30 to 50 Percent

Announcing OrCAD 16.6—A One-Two Punch for Mainstream PCB Engineers

Cadence Allegro Accelerates Product Creation Through Efficient Collaborative ECAD Environment Using Microsoft SharePoint

Allegro 16.6: Easing PCB Design for Multi-Gigabit/Second Signals

What’s New in Cadence OrCAD 16.6 Release  

Cadence Releases OrCAD 16.6, Boosts PSpice Performance By Up to 20 Percent

I’ll be blogging about some of the most helpful product features over the coming months, but here are just some of the new 16.6 capabilities that will increase your design productivity…

Allegro PCB Editor

  • Support for embedding components with dual-sided contacts and vertical components on the inner layers of a PCB
  • New embedded cavity DRCs
  • Faster timing closure with auto-interactive route delay tuning (AiDT)
  • PCB Team Design Option accelerates design implementation
  • Auto-interactive pin-swap (“Planning Mode”) for FPGAs within Allegro PCB Editor using Allegro FPGA System Planner under-the-hood
  • Offset routing allows users to route off-orthogonal angles to avoid coupling high-speed signals with substrate glass fiber-weaves
  • New Slide function
  • Export / Import design data to and from manufacturing using the open industry-standard IPC-2581
  • New artwork control form allows users to assign film record classes and subclasses to a film record
  • General Edit Application Mode allows users to assign a single region constraint to multiple region shapes
  • Align components by edge (top, center, bottom) using DFA constraints or equal spacing (controllable by user-defined equal spacing and + and - buttons)
  • Support for text in Place Replicate
  • Quickplace allows component overlap (user-defined % overlap) to get the components on the board faster
  • Refresh a symbol by instance
  • New command allows users to add rectangles with parameterized corners (champhered, rounded, or orthogonal)
  • Dynamic shape allows thermal width for cross-hatch shapes based on the cross-hatch line width
  • New display option overlays net names along cline path, pins, shapes, and flow lines
  • Lines and text can now be moved outside their present class-subclass structure
  • Select objects by “Lasso” or “path”
  • Highlight or de-highlight nets associated with a component
  • DRC can now be run “by window” when online DRC is turned off
  • Specify any text for the associative dimension value using the optional Text filed in the Options tab
  • Specify separate output files for plated versus non-plated (NC) routing
  • Pastemask-to-pastemask DRC will check the “Package Geometry - Pastemask_Top” shapes within the same symbol
  • and more …

Allegro Package Designer

  • Shape Shorting - Via Array
  • Bondwire Text In
  • Wirebond Application Mode
  • Assembly Design Rule Check (ADRC)
  • Open Cavities
  • Geometry to Symbol
  • and more …

Allegro PCB SI

  • Setup/Audit Enhancements
  • SigXP Via Enhancements
  • Auto-solving Models in SigXP
  • Channel Analysis Enhancements
  • PDN Enhancements
  • PDN DeCap Management
  • and more …

Allegro RF SiP

  • Library Manager Flow Improvements
  • Support for curves in RF Shape Routing
  • Bond Wire Retain Flow
  • and more …

Allegro RF PCB

  • Improvements to importing from Agilent ADS to Allegro Design Authoring
  • Support for new ADS RF etch elements libraries
  • Snap improvements
  • “Add Connect” allows users to connect to the edge of a pad, or overlapping a pad
  • Scaled copy allows snap to pad edge
  • Unnecessary DRC errors removed when netlist is imported into Allegro PCB Editor
  • Via exchange between ADS and Allegro environment
  • and more …

Allegro Design Entry HDL

  • Interface Aware Design (Netgroups)
  • Split hierarchical symbols and support for hierarchical nets in the Cross Referencer enable team design on designs with large pin-count components like microprocessors
  • Constraint comparison utility allows users to compare constraints from two HDL schematics, PCB designs (brd), modules, and constraint files (dcf)
  • Enhanced object filtering and visibility in the Constraint Manager, plus an option to use higher level net names for Xnet naming
  • and more …

Allegro FPGA System Planner

  • Support for additional FPGA architectures from Actel (ProASIC3), Altera (Cyclone V, Stratix V), and Xilinx (Virtex 7)
  • Auto-interactive pin-swap (“Planning Mode”) for FPGAs within Allegro PCB Editor using Allegro FPGA System Planner under-the-hood
  • Support for new termination schemes
  • Design Compare
    and more …

Allegro Design Workbench

  • Team Design Authoring solution now provides work-in-progress design data management and an efficient collaboration environment using SharePoint 2010
  • Comprehensive library model management for logical schematic blocks and physical modules
  • Configuration Manager Enhancements
  • Design Migration Enhancements
  • Flow Manager Enhancements
  • and more …

Allegro Design Entry CIS

  • OrCAD Schematic – Signal Integrity Flow
  • Enhanced Save Function for Design and Library
  • Enhancements in the Find Function
  • Enhancements in Cache Updates
  • Project Save As Enhancements
  • NetGroup Enhancements
  • Design Level Auto-RefDes
  • Locking Reference and Designator Properties
  • Design Rule Check (DRC) Enhancements
  • Full RefDes support
  • CIS – Link Database Part
  • and more …

Allegro AMS Simulator

  • Advanced Options
  • Probe DAT Version Upgrade - 64-Bit Data Precision
  • Undo Support for Capture Netlists
  • Enhanced IBIS Support
  • Multi-Core Engine Support
  • Configuring Menus and Toolbars
  • Encryption Enhancements
  • New Models
  • and more …

As always, I’ll look forward to your feedback on how you’re using these new 16.6 capabilities!

Jerry “GenPart” Grzenia


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.