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What's Good About Allegro GRE Embedded Component Support? It’s in the 16.5 Release!

Comments(0)Filed under: PCB Layout and routing, PCB design, SPB, Allegro PCB Editor, High-Density Interconnect, HDI, Allegro, PCB Editor, PCB, layer stacks, layout, GRE, global route, design, routing, High Speed, SPB16.5, Allegro 16.5, embedded components

Just a quick post today …

The Allegro Global Route Environment (GRE) has been enhanced in the 16.5 release to support embedded components.

To expand Allegro's usability in the High Density Interconnect (HDI) environment, GRE has been enhanced to understand Embedded Components. This functionality is basically transparent to the designer in an Allegro flow. You just need to design and route normally.

However, there are a few minor things you need to be aware of:

  • Fanout must still be done for routes that are not on the same signal layer as the pins of the embedded component.
  • About placement and routing of components on internal plane layers:
    • Allegro allows placement of embedded components on plane layers. However, GRE will not route to them.
    • As of now this is not a supported model.



Please share your thoughts on this new 16.5 capability.

Jerry “GenPart” Grzenia

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