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What's Good About Allegro GRE Constraint Region Support? It’s in the 16.5 Release!

Comments(0)Filed under: PCB Layout and routing, PCB design, Allegro PCB Editor, Allegro, PCB Editor, PCB, layout, "PCB design", GRE, routing, SPB16.5, Allegro 16.5, constraint region

The 16.5 Global Route Environment (GRE) now allows or prohibits tuning in constraint regions.

This functionality was designed to help PCB designers prevent delay routing in constraint regions. This is generally desirable as the space is so tight in the BGA via field that there is little room and what little there is -- is needed for routing. In addition to a space problem, the vias break up the plane with a lot of voids that allow the routing to 'leak' EMT through these holes or allow the routes to 'de-reference' from the plane which just increases a routes ability to radiate.

But, this functionality can also be used in free areas of the design to 'prevent' delay routing in constraint areas. In other words, if you have a constraint region and routes pass over it on an adjacent layer, you could reduce the amount of coupling by using a constraint region with 'standard' PCB level rules.

Read on for more details…

Process

There are several ways to control this behavior
    - at the global level in Design Parameters, or
    - at the Bundle level on its own properties.

Setup> Design Parameters> Flow Planning> Routing Controls
Chose 'Allow in constraint areas' either Yes or No



 

Another method:

RMB on the bundle and select 'Bundle Properties':


 
 
Tuning Allowed in Constraint Area:



 

Tuning not allowed in Constraint Area:



 

Check out the Video of this capability

As always, I welcome your feedback on this new 16.5 feature.

Jerry “GenPart” Grzenia

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