Home > Community > Blogs > PCB Design > what s good about allegro pcb router inset vias see for yourself in 16 5
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the PCB Design blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

What's Good About Allegro PCB Router Inset Vias? See for yourself in 16.5!

Comments(0)Filed under: PCB Layout and routing, PCB design, Allegro PCB Editor, High-Density Interconnect, HDI, Allegro, via, PCB Editor, PCB, layer stacks, layout, "PCB design", design, routing, High Speed, SPB16.5, Allegro 16.5, interconnects, inset vias

Another high density interconnect (HDI) technology that has gained popularity is inset vias. The 16.5 release has provided new commands added in Allegro PCB Router to support inset vias.

Via in Pad pattern has been very popular due to its clear advantage of offering lower parasitics as compared to other fan-out patterns like dog bone patterns. But, it may pose a challenge for the assembler to deal with the trapped air, especially under the BGA balls. Inset patterns solve this and also provide the advantage of reduced parasitics as compared to dog bone pattern.
Inset pattern consists of two vias connected to each other by overlapping their pads:


The amount of overlap is constrained by samenet clearance between net based hold and pads of bbvias forming inset construction.

Read on for more details ...

Notice the changes in the clearance descriptor syntax, especially the tangency and inset rules at bottom:


For details on this syntax please refer the Allegro PCB Router command reference manual.

Translating Inset rule from PCB Editor / SPIF Changes

BBVia inset configuration in Allegro PCB Designer is recognized like bbvia to bbvia samenet clearance value specified to -1. The rule is accounted in via configuration creation where even samenet DRC checker is turned off, and both core bbvia and microvia types are affected. SPIF will replace -1 clearance values for this type with specific keyword “inset” that inform SPECCTRA about inset configuration on all hierarchy levels.


The following sets a rule at design level which specifies the inset rule between bbvia and bbvia -
rule PCB (clearance inset (type bbvia_bbvia))

The following sets a rule for net D0 which specifies inset rule -
rule D0 (clearance inset (bbvia_microvia))

Highlight Inset Vias

You can now highlight the inset vias by using the highlight command in SPECCTRA.

highlight via_inset on

This will highlight the inset vias as shown below:


highlight via_inset off

This will remove the highlight of inset vias.

I look forward to your comments about this capability.

Jerry "GenPart" Grzenia


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.