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Scores of PCB Designers Gather for Free Signal Integrity Event

Comments(0)Filed under: PCB Signal and power integrity, PDN, DDR3, IBIS-AMI, Allegro, SI, PCB, PCB Signal integrity, PCI Express, power integrity, PI, Allegro 16.5, OrCAD PCB SI, signal integrity, Robert Hanson

On day-one of the Cadence PCB Signal and Power Integrity Three-Day Event, over 100 professionals gathered in the auditorium at Cadence headquarters eager to learn from Robert Hanson’s presentation on Signal Integrity basics.  The presentation started with the Fundamentals of Signal Integrity and moved on to transmission lines, crosstalk, termination strategies, and concluded with the effects of vias on high speed signals.  The day finished off with a presentation of how Cadence PCB signal integrity products can be used to analyze these effects on designs with which the attendees are currently working.

The response for this event was tremendous with all seats reserved within two weeks.   Many of the attendees had wanted to attend a signal integrity (SI) class, but knew that acquiring budget to do so would be difficult.  So, when a free event with industry renowned SI educator Robert Hanson was made available, they signed up right away.  Many noted that Robert’s teaching style made the topic fun and enjoyable.

                                                                         SI Event Day1         

Chinh Tran, Account Manager of Technology at Cadence said, “Many of my customers are facing signal and power integrity issues.  Because their day to day responsibilities vary greatly, it is not always easy to focus on the cause of the issue.  Our Three-Day Event is just the refresher course they have been looking for.”   Cadence offered to sponsor Robert Hanson for the three-day event in order to give PCB design customers additional background in signal and power integrity.  Effective debugging of SI and PI problems using analysis tools is greatly enhanced when one has some background in the science.  Robert has been providing this background to people involved in PCB design for over 25 years, so Cadence was thrilled to collaborate with Robert and offer an abbreviated version of his five-day course material at the event.

Day two and day three will dig deeper into signal and power integrity issues with a focus on high speed DDR3 memory interfaces, multi-gigabit serial link design, and efficient design of power delivery networks.  Cadence PCB analysis tools have been through recent upgrades to provide enhanced capabilities in these areas.  Many of the attendees on day two and day three will be given the opportunity to experience these improvements with a hands-on workshop that will take place after Robert goes through his educational material.

The event was planned with the purpose of providing a mix of education and theory with hands-on practical design tool use experience.  Tell us about your experience at the Cadence PCB Signal and Power Integrity Three-Day Event.


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