At the Electrical Performance of Electronic Packaging and Systems conference (EPEPS 2011) in San Jose, Calif. Oct. 23-26, Cadence will demonstrate our latest technology developed for PCB multi-gigabit design and analysis. Join the buzz at Table 8 while the exhibits are open on Monday and Tuesday (10/24-10/25), as our product experts will be available to discuss and demonstrate 3D Full-Wave Analysis Technology integrated into the Allegro PCB SI design and analysis environment. This demonstration will be the perfect introduction to the embedded tutorial on Wednesday morning where Cadence and the University of Illinois at Urbana-Champaign (UIUC) will jointly discuss the need to combine 2D and 3D extraction technology for accurate, yet efficient, modeling and analysis of multi-gigabit signals.
The Wednesday morning (8:00 a.m. – 8:50 a.m.) tutorial is titled, “Fundamentals and Advances in Full-Wave Characterization of Interconnects for PCB Signal Integrity Applications” and will be presented by Dr. Jian-Ming Jin from UIUC, along with Dennis Nagle and Jilin Tan from Cadence. This tutorial will discuss current design trends and challenges along with the pros and cons of various methods of performing EM characterization.
While the emphasis will be on fundamentals, the tutorial will also present practical and automated full-wave modeling methodologies for PCB interconnect. Cadence technologists will also be hosting discussions at the Monday afternoon Poster Session as they present their research on “Three Finite-Element Time-Domain–Based Numerical Algorithms for High-Frequency Broadband PCB Simulations” and “A Comparison of Two Latency Insertion Methods in Dependent Sources Applications.”
We look forward to connecting with you at EPEPS. Please say hello at our demonstration table and feel free to leave your comments here on what you liked about Cadence at EPEPS.