The 16.5 release of the Allegro System Connectivity Manager (SCM), also known as Allegro System Architect (ASA), has been enhanced to view implicit power pins in the Component Connectivity Pane (CCP).
This is required for control over the power pins for the design with dies or FPGAs where an ECO is required. This is also required in the co-design flow for SiP where connectivity changes are updated using the ECO Netlist.
Limitations (pre-16.5) without using visible power pins are:
- Connectivity of power pins is lost in ECO Die Import as the implicit power pins are not mapped.
- Changes in the power pin names of a part, the import connectivity to power pins is lost.
- Power pin connectivity gets lost during an Import ECO Netlist.
Read on for more details …
You have the option of viewing the power pins explicitly in the Component Connectivity Pane.
This option can be controlled from:
Project> Settings> General tab
Select the option 'Show Power Pins in Connectivity Pane'
The project .cpm file directive to control this is:
By default, the value is ‘ON’.
When this option is not enabled, the Component Connectivity Pane details look like this:
When the Show Power Pins in Connectivity Pane option is enabled, the power pins are visible in the connectivity pane. The value for Pin Name is derived by the power pin definition in chips file and the Pin Type column shows the pin use – Power/Ground. The power nets attached to the power pin of the component are updated in the CCP:
The Assign Power option is disabled once power pins are visible in CCP. If this option is not enabled, assignment of power pins is through the Assign Power form. In SCM, select an instance in the Component List Pane (CLP) and then Object> Assign Power...or use the RMB menu > Assign Power...
You can connect any type of signal to the power pins. The connection count is updated automatically and the signal names are italicized in the Signal column. The modified connection will appear in normal font and is not italicized (notice the difference between signal 'TEST' and 'VCC'):
These connections are stored as internal properties - POWER_PINS, POWER_GROUP.
You need to add voltage values to the nets when connecting power pins. If a voltage is not added, you will get this warning message while saving the design:
It is advisable to enable the option "Show Power Pins in Connectivity Pane" before you start constructing a new design.
Please share your experiences with this new 16.5 feature.
Jerry "GenPart" Grzenia