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What's Good About APD’s Assembly DRCs? You’ll Need the 16.5 Release to See!

Comments(1)Filed under: PCB Layout and routing, PCB design, SPB, Allegro, advanced package designer, PCB Editor, APD, IC Packaging, PCB, DRC, ADRC, layout, "PCB design", SPB16.5, Allegro 16.5, assembly DRCs

Prior to the Allegro Package Designer (APD) 16.3 release, Design Rule Check (DRC) markers created by Assembly Rule Checks had to be external DRC markers since no constraint IDs were associated with the ADRC constraints.  In the 16.3 release, Constraint IDs were created for each of the rules. It enabled us to make a change to DRC markers.  For the 16.5 release, each Assembly DRC (ADRC) rule gets its own marker based on constraint ID. 

APD’s ADRC DRC markers will look and behave similar to all DRCs. ADRC markers will differ for different rule checks (or groups of related rule checks), rather than all appearing the same as it was with using External DRC markers.  ADRC DRCs will have their own worksheet in Constraint Manager instead of being combined with External DRC markers.

Differences between current (external) DRC behavior and constraint ID based behavior are as follows:

 

CURRENT

CONSTRAINT ID Based

Comments

When object that has DRC Marker attached is moved

DRC Marker stays at previous location (unattached )

DRC marker deleted

( without warning)

This will display the message that the disappeared marker doesn’t mean that there is no error any longer, just that the ADRC rules have to be re-run.

Update DRC command

Doesn’t have any effect on ADRC DRC markers

Doesn’t have any effect on ADRC DRC markers

Update DRC will not affect ADRC DRC markers, similar to batch DRCs run by the rest of the system 

When object that has DRC Marker attached is deleted

DRC Marker  deleted

DRC Marker  deleted

No change in behavior

Reports > DRC report

Reports ADRC DRCs as any other in the system

Reports ADRC DRCs as any other in the system

No change in behavior

 

Read on for more details ...

 

Show element difference


16.3:

 
Constraint ID based in 16.5:

 

DRC marker difference

16.3:

 
 
16.5:

 

DRC marker 2 letter combinations
 
Lower case letters for 2 letter combinations are used for the DRC bow-tie marker.  
Existing online wire rules already have 2 letter combinations and they are upper case letters. 
They are:

 

Wire Length ( minimum)

WA

Wire Length ( maximum)

WI

Wire Maximum Angle to Die Edge

WA

Finger to Component Spacing

FC

Wire to Finger Spacing

WF

Wire to Pin Spacing

WP

Wire to Wire Spacing

WW

Wire End to Wire End Spacing

WE

 

 There are no changes to existing DRCs.

 ADRC batch rule combinations:

Group

Rules in the group

2 letter combination

Wire Physical

Wire Length over Parent Die

wl

Wire Physical

Wire Length over Lower Die

wl

Wire Physical

Wire Maximum Angle to Finger

wa

Wire Spacing

Wire Substrate End Distance inside soldermask

ws

Wire Spacing

Wire to Component Spacing

wc

Die Physical

Die Overhang

oh

Die Physical

Die Pad Pitch

pp

Die Physical

Die Pad To Lower Die Overhang

oh

Die Physical

Die Pad to Upper Die Spacing

pd

Die Spacing

Die to Connected Finger Spacing

df

Die Spacing

Die To Finger Spacing

df

Die Spacing

Die to Package Edge Spacing

de

Die Spacing

Die To Die Spacing, Connected Dies

dd

Die Spacing

Die To Die Spacing, Unconnected Dies

dd

Optical

Wire to Die Pad Optical Short

os

Optical

Wire to Finger Optical Short

os

Optical

Wire To Wire Optical Short, Die to Die

os

Optical

Wire to Wire Optical Short, Die to Substrate

os

Die Stack

Center to Center Delta, Extends Based

cc

Die Stack

Center To Center Delta, Pin Based

cc

Die Stack

Die Stack Height

sh

Die Stack

Die Stack to Die Stack Spacing

dd

Die Flag

Die Flag to Die Flag Spacing

xx

Die Flag

Die Flag to Discrete Component Spacing

xc

Die Flag

Die Flag to Finger Spacing

xf

Die Flag

Die Flag to Package Edge Spacing

xe

Solder Mask

Continuous Solder Mask Coverage

sm

Solder Mask

Minimum Solder Mask Shape

sm

Solder Mask

Minimum Solder Mask Void

sm

Solder Mask

Solder Mask To Die Edge Spacing

sd

Solder Mask

Solder Mask to Package Edge Spacing

se

Solder Mask

Solder Mask To Solder Mask Spacing

ss

Package Substrate

Any Metal To Any Metal Spacing

mm

Package Substrate

Cline to Via Overlap

vo

Package Substrate

Conductor to Package Edge Spacing

me

Package Substrate

Discrete Component Pad to Finger Spacing

pf

Package Substrate

Discrete Component Pad to Package Edge

pe

Package Substrate

Exposed Metal to Exposed Metal Spacing

mm

Package Substrate

Finger to Package Substrate Spacing

fe

Package Substrate

Minimum cline segment

cs

Package Substrate

Trace Extension from Finger

te

Package Substrate

Via to Package Substrate Edge Spacing

ve

Shape

Acute Angle Shape Boundary

aa

Shape

Minimum Shape Check

ms

Shape

Minimum Void Check

ms

Acute Angle Metal

Acute Angle Routing

aa

Acute Angle Metal

Merged Metal Minimum Angle

aa

Acute Angle Metal

Trace Minimum Angle to Pad

aa

Acute Angle Metal

Trace Minimum Angle to Shape

aa

Acute Angle Metal

Trace Minimum Angle to Trace

aa

Miscellaneous

Conductor Shape Void Overlap

vo

Miscellaneous

Degassing Void Overlap

vo

Miscellaneous

Tombstone Check

ts

 

DRC Display in Constraint Manager

New Assembly Worksheet in the DRC domain of the Constraint Manager where assembly DRCs will be displayed:

 
Note: Uprev and downrev will remove all existing ADRC DRC markers and display a message in the console (as well as in the uprev/downrev log file) to run ADRC again.

Please share your experience using this new capability.

Jerry "GenPart" Grzenia

Comments(1)

By Norocel Codreanu on August 1, 2011
APD is a design environment focused to a very "hot" topic today, the design and management of bare dies and electrical connections of them in the frame of advanced packages (SIP – System in Package, SOP - System on Package) and vertical stacked dice. A System-in-a-Package or System in Package, also known as a Chip Stack MCM, has a number of integrated circuits enclosed in a single package or module. The SIP performs all or most of the functions of an electronic system. System-On-Package (SOP) is the newemerging system technology that goes beyond System-On-Chip (SOC) and System-In-Package (SIP) and forms the basis of all emerging digital convergent electronic and bio-electronic systems.

The 16.5 APD addresses improvements of Assembly DRC (ADRC) rules, the new version increasing the capabilities to manage the errors and markers. For example, each Assembly DRC (ADRC) rule receives now its own marker based on a "constraint ID" in the Constraint Manager. In case of markers, the ADRC markers differ in 16.5 for different RC (rule checks) or groups of RCs. The ADRC markers have now a "personal" worksheet in the Constraint Manager, helping the designer to manage better the real cases and to understand easier the various problems which could appear in practice.

Furthermore, for electromagnetic investigation of dice and stacked-dice different methods could be used, as 2.5 D (3D layered) simulators based on Method of Moments or more general FEA simulators. The electromagnetic simulators offer today reliable results of SIP/SOP structures and help additionally the specialists using Cadence APD.

As a conclusion, APD 16.5 provides now a better interface with the designer in the field of ADRCs and management of errors and markers.


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