Home > Community > Blogs > PCB Design > what s good about allegro pcb router region rules 16 5 has a few new enhancements
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the PCB Design blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

What's Good About Allegro PCB Router Region Rules? 16.5 has a few new enhancements!

Comments(3)Filed under: PCB Layout and routing, PCB design, Allegro PCB Editor, Allegro, PCB Editor, PCB, layout, "PCB design", global route, design, routing, Constraint-driven PCB Design flow, SPB16.5, Allegro 16.5

Designers normally create nets or groups of nets to assign constraints. This leads to nets rules, net class rules, and net class to class rules. As the size of physical symbols (footprints) is reducing, the need for region specific rules is also increasing.


When all these constraints are applied, the amount of memory consumption by the Allegro PCB Router increases. In 16.5, proper use of Net class and Net-class to class rules and region rules can significantly reduce the memory consumption.


Read on for more details…

Until 16.3, each region specified in Allegro PCB Editor was defined separately for each layer in the Router. The same applied for the Region Class. For example, on a board with 20 signal layers with only net rules defined, the corresponding do file would have 20 lines which would define a region for each layer. The numbers would multiply with net class and net class to net class rules.


Region Definition Syntax

In 16.5, SPECCTRA has been enhanced to handle region rules for all signal layers or specified layers.
This figure describes the "define region" syntax:

 



Smaller Data Files

Take an example of a very simple region defined on all layers in Allegro PCB Editor in the SPB16.3 version and exported to the Router. The region definition was done on each layer as shown below:

 

Now take a look at the definition of same region in the 16.5 version:

 
In addition, prior to the 16.5 release, the constraints were defined for each of the layer specific regions. In this example, the constraints become more simplified as they need to be defined only on one region.


Faster Routing


The auto router has been enhanced to understand the new region definitions and route accordingly. This leads to much less memory consumption and much faster routing.


Performance Improvement -Sample Test Results:

 

Key Points Using Region Rules

  • Multiple regions that have same X-Y Coordinates and layer ranges are merged.
  • Rules assigned to each region apply to overlap area.
  • Higher level rules in Rules hierarchy take precedence.
  • When multiple rules applied at same level of hierarchy the last rule read "Wins".

 

 

As always, I look forward to your comments regarding these improvements.

Jerry "GenPart" Grzenia

Comments(3)

By Norocel Codreanu on July 4, 2011
The enhancement is very useful for very high number of multi-layer PCB and minimizes dramatically the file for the PCB Router. The "region rule" can be applied also to classical 6L-PCB, 8L-PCB or 10L-PCB, optimizing the design time.
I consider this is a strong feature for complex, multi-layer boards.
Norocel Codreanu

By ARAVINDA D.S on August 19, 2012
i want some details of pcb  editor of footprint creation details please make some guide of footprint creation of different parameters


By Jerry GenPart on August 20, 2012
Hi

There's some good documentation available here -


support.cadence.com/.../cos;q=algrolibdev/algrolibdev16.3/algrolibdevTOC.html
 

There's also a training course available:


support.cadence.com/.../cos=Training/Datasheets/allegro-pcb-librarian-v16.5-(ils).html

Jerry G.

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.