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DDR3 Design-in Challenges Tackled by SoC Realization With Allegro PCB SI

Comments(0)Filed under: DDR3, PCB, TeamAllegro, SPB16.5, Allegro 16.5, EDA360, TimingDesigner, SoC Realization, bus analysis, design-in kit, memory IP

Allegro 16.5 is another step forward for Cadence towards the realization of the EDA360 vision. Part of that vision is System-on-Chip (SoC) Realization, and SoC Realization requires a broad-based, comprehensive solution for memory and storage IP. 

Because applications used on all types of handheld, desktop, and rack mounted platforms require faster access to data, memory interfaces are key elements for delivering on the EDA360 vision.  While Cadence was first to market with a DDR4 IP solution for SoC design, the latest memory roadmaps indicate that DDR3 will continue to advance in both performance and reduced power consumption for several years to come.

Cadence DDR4 IP Solution for SoC

So, while forward-thinking designers and integrators are building architectures to support the emerging DDR4 standard, products being designed today will continue to use DDR3.  It is for this reason that adopters of Allegro 16.5 will benefit greatly from the investment made around easing the design of memory interfaces, especially DDR3.
The Cadence solution for DDR3/DDR4 is differentiated in that it includes design and analysis beyond the chip, and into the package and board.  The Allegro 16.5 release includes many improvements for DDR3 design and analysis of PCB memory interfaces.  These improvements are grouped into three areas, 1) PCB design and analysis tool enhancements, 2) integration with TimingDesigner (provided by EMA-EDA), and 3) a design-in methodology kit including a half day workshop to jump start designers needing to rapidly come up to speed on the DDR3 design-in methodology.

One notable tool improvement is post-route bus analysis.  The extensive report file is now much easier to read, and allows the reader of the report to focus very quickly on problem areas.  In addition, there is greater flexibility in the way derating tables are read, insuring that including this important timing information is accomplished with greater ease.

Integration with TimingDesigner brings a comprehensive, two-vendor timing solution to the hands of Allegro users.  The bus analysis report file is read directly into the DDR3 templates available for TimingDesigner.  Timing violations can be quickly located and what-if scenarios can be evaluated to strategize on the best way to resolve any timing violations.

And finally the DDR3 design-in methodology kit, optionally delivered as a workshop, guides Allegro users through early design planning through final signal quality and timing closure.  You can contact your local Cadence Sales representative to learn how to sign up for a DDR3 methodology workshop today.


Contents of DDR3 design-in methodology kig

We look forward to your comments and observations on Allegro 16.5 and the complete Cadence DDR3/DDR4 memory interface solution.



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