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What's Good About Vias And The Allegro Router? SPB16.3 Has A Few New Enhancements!

Comments(6)Filed under: PCB Layout and routing, PCB design, Allegro PCB Editor, Allegro, via, microvia, PCB Editor, PCB, SPB 16.3, Allegro 16.3, layout, "PCB design", SPB16.3

A few new enhancements specific to vias in the SPB16.3 release of Allegro PCB Editor have been introduced. The are called use via region and stacked via support.

Use Via Region

Many times you need to restrict usage of specific vias in a region. Allegro PCB Router has been enhanced to allow via usage in a certain region.
The use_via rule has been enhanced to align with the Allegro via list functionality. The following objects support the use_via rule:

1.    region
2.    region net
3.    region class

Stacked Via Support

In the SPB16.2 version, stacking rules were only supported at the design level. The SPB16.3 release extends the via stacking rules to all hierarchy levels in Specctra. It also supports the exclusive microvia stacking capability provided in Allegro PCB Editor. 

Read further for more details ...

Use Via Region

The new physical rules look like the following:
circuit region <region_name> (use_via {[<padstack_id>]})
circuit region_net <region_name> (use_via {[<padstack_id>]})
circuit region_class <region_name> (use_via {[<padstack_id>]}) 

Specifying Vias for a Region

Via rules can be specified in the Allegro Constraint Manager.  Open Constraint manager > Physical > Region > All Layers and select the vias for regions. The rules specified in Constraint Manager are transferred to the Router. The rules are translated to a "do" file.

Reports

Use via conflicts should be reported as a type option to the 'report conflict' command:
report conflicts window (type use_via)
If any conflicts exist, they are reported according to the syntax:
#1: Incorrect Via Padstack Usage "VIA019" 

Stacked Via Support

Exclusive Microvia Stacking


Via rules can be specified in Allegro Constraint Manager.  Simply go to Constraint manager > Physical > Region > All Layers and select the vias for regions. The rules specified in Constraint Manager are transferred to the Router.




The above shown Pad-Pad Connect rule, if set to MiCROVIAS_MICROVIAS_ONLY, is translated to the Allegro PCB Router as below:
rule net A2 (stack_via exact microvia_only)
Syntax:
<stack_via_descriptor>::= (stack_via on | off | exact | any_overlap [microvia_only | bbvia_only])

on : Turns on stack_via, which allows vias to stack.
off : Turns off stack_via, which means vias cannot be stacked.
exact: This is default option; specifies that vias are placed coincidently on contiguous layers acting as a single vias.
microvia_only: Specifies that stacking is allowed for micro via objects only.
bbvia_only: Specifes that stack contains only bbvias.

If only the stacking rule values is on then stacking is allowed to any combinations of bbvia and microvia..

Example of layer rule particular layer:
define (class CLASS1 (layer_rule SIG1 (rule (stack_via on) ) ) )
The above rule means that bbvia and uvia stacking is enabled for layer SIG1 for class CLASS1.

Rule hierarchy for stack_via


In SPB16.2, Specctra was supporting via stacking rules only at the PCB level. SPB16.3 allows specifying the via rules at  most of the physical levels. The via stacking rule is applied to the levels in Allegro Physical rules hierarchy outlined below:


The highest prioirty is for a region class and the lowest is for design level.

Note:  xnet level is not supported and will not be translated by SPIF.

Stack via depth rules are specified in Specctra directly and not imported from Allegro. Depth rules are specified for objects (but not on layer level for objects).

The primary change in stacking via usage is on enabling the rule on layer basis.

Class A has the following stacking rules defined.

define (class A (layer_rule SIG1 (rule (stack_via on microvia_only) ) ) )
define (class A (layer_rule SIG3 (rule (stack_via on microvia_only) ) ) )
rule class A (stack_via_depth 3)

The above example enable microvia stacking only for ClassA on specified layers, while in earlier implementation you would need to enable stack_via rule for all layers.

Reports

Specctra reports have been enhanced to reflect the new functionalities. The rules report and the conflicts report have been enhanced as shown below.

Rules report: When via stacking is enabled for an object, it is reflected in the reporting. The possible values for the state are the following:

"off" – if via stacking is forbidden
“exact” – if any via type stacking is allowed
 "any_overlap" – if any bbvia/uvia coincident combination allowed
"microvia_only" – if microvia coincident combination allowed only
 "bbvia_only" - if bbvia coincident combination allowed only
 "microvia_only with any_overlap option" – if microvia coincident and non- coincident combination allowed only
"bbviawith any_overlap option" - if bbvia coincident and non-coincident combination allowed only


For a depth-based approach it looks like the following:
                 Stack Via = exact
                 Stack Via Depth = 3

Conflict reports: Stack via violations are reported in “Report Conflicts - Route” .
 

As always, I welcome your feedback on how you're using these new features.

Jerry "GenPart" Grzenia

Comments(6)

By Hemanth on June 25, 2010
Hi Hello I am using Allegro Pcb Router i know upto create project and create netlist please tell me how to create footprint and how to import to pcb board file and routing ..............................
Thanking you
With Regards
Hemanth J

By Jerry GenPart on June 25, 2010
Hi Hemanth,
The process you describe is part of the standard design flow and it's covered in our training courses. You can review training courses offered here - www.cadence.com/.../training_catalogs.aspx
Also, there are a couple tutorials available that cover the details of what you're trying to accomplish. These ship with the software and can be found in the Tutorials folder of the Start menu (on the PC).
Jerry

By LUCIANO on July 25, 2010
hi i'm new begener user PCB design, i have done a lot of year ago any experiance with release 4 and 5 PCB but i notice is all change naturally but any experiance i remember

for old release software but now i want to explain my problem about new release that is

kindly but i dont know where i can place any component in my board.

Other release i remember that was necessary create first step layout or dimenson of board   and than was possible place component but now i dont know where i can exactly step to create board and i dont know where i can charge al component o library

to place on board

thank you very much


By Jerry GenPart on July 26, 2010
Hi Luciano,
You're on the right track. You need to make a board outline and define the placement area - then you can begin placing parts. My suggestion to get you up-to-speed quickly with the current release is to review the Allegro PCB Editor Tutorial that's available with your Cadence installation.
Jerry

By Mark Garcia on January 5, 2012
I have a question about stacked vias. Is there a way to merge a micro via to a blind via?
I are using micro vias on both sides of the board. On the top side we are dropping down
1 layer to a fanout pattern using blind vias. And on the bottom we are stacking a micro vai on top of the blind via. Can we merge the blind via to the micro via so we don't have to drop 2 vias every where?

By Jerry GenPart on January 5, 2012
Hi Mark,
I asked our Allegro PCB Editor Support AE experts about this. They don't believe this can be done within the core Allegro PCB Editor tool. It may be possible to do this using an Allegro SKILL routine.
Jerry G,

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