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DDR3 Timing issues? Watch the Allegro PCB SI / TimingDesigner Webinar!

Comments(5)Filed under: PCB Signal and power integrity, DDR3, SI, Signal Intregrity, SPB 16.3, Allegro 16.3, PCB SI, IBIS, "PCB design"Last year, TimingDesigner improved the interface to PCB SI and many of our joint customers have taken advantage of performing static timing analysis on their fully routed boards using the two tools together. However, DDR3 adds a whole ’nother level of complexity with its faster speeds, lower voltages, programmable ODT, derating tables, write leveling, and on and on.

Fortunately, the folks working on TimingDesigner and PCB SI have been in close touch with each other and now provide a seamlessly integrated solution that allows straightforward timing closure on even the fastest DDR3 memory interfaces. When timing violations are found, changes can be performed on the PCB design and re-analyzed without any translation making this two tool combination the fastest path to timing closure.

Due to repeated requests for such a solution, a joint company (Cadence and EMA) webinar will be broadcasted and recorded on June 9, 2010. Please register at your earliest convenience so that you will not miss the opportunity to watch and ask questions. Additional information and registration is available from this link.

Let us hear your feedback on the webinar.


TeamAllegro

Comments(5)

By waqar on May 30, 2010
what is the porcedure

By Maxwell86 on May 31, 2010
Hi Waqar - We hope you will watch the webinar ... you will see the step by step procedure on how to use PCB SI and TimingDesigner to analyze and verify timing on DDR3 interfaces.

By randydawson on June 30, 2010
When will it hit the archive, I missed it, heck.

By Maxwell86 on August 4, 2010
Hi Randy - the recorded webinar can be accessed at this address ... www.cadence.com/.../event.aspx
Hope to hear your feedback on the webinar.

By strangluv on May 28, 2013
This is perfect for us!  Maxwell86, does Timing Designer interface with the new Sigrity tools?


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