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What's Good About Taray? Quite a Bit Actually!

Comments(1)Filed under: PCB design, Allegro, OrCAD, FPGA, FPGA System Planner, Taray

You've probably read about all the buzz in the EDA news this week -

"Cadence acquires FPGA-focused EDA startup" and here.

"Cadence buys Taray in time for 28nm FPGAs"

"Cadence Acquires FPGA Tool Firm Taray"

"Cadence acquires Taray (why did it take them so long?)"

Of course, the Taray "7 Circuits" FPGA optimization technology had been integrated into the Cadence OrCAD and Allegro FPGA System Planner (FSP) more than a year ago and there will be continued enhancements made to both the core technology and FSP.

Some key takeaways from the press announcements this week:

"We knew upfront that FPGA was becoming much more of an issue in the PCB space. FPGAs are growing in complexity. They are having much more capability in terms of ARM processor cores, high speed interfaces for example, and we are seeing more people turning to FPGAs than trying to develop ASICs or SoCs themselves. So, we saw that as a good sign that FPGA is becoming more of a decision criterion for companies purchasing PCB software," commented Keith Felton, Cadence's group director, Product Management Allegro and OrCAD PCB, IC Packaging and System-In-Package Technologies. He added: "The Top 5 customer request from around the world is for Cadence to have a powerful, integrated methodology for designing these complex FPGAs into a PCB. FPGA design-in gives Cadence a tremendous opportunity to provide differentiation in the marketplace. This is the reason why we moved from an exclusive OEM agreement [with Taray] to an acquisition." "We've never released a PCB tool that was adopted as quickly as this," Felton said.

Hemant Shah, product marketing director at Cadence, highlighted three characteristics that make Taray's 7Circuits technology unique in the marketplace. He started: "Bringing the three domains together in one common environment, the FPGA PCB codesign environment, it brings the FPGA knowledge and the layout information all in one place. That does not exist in any other solution on the market." Secondly, he continued, once you have these three things in the environment, the synthesis engine takes the users' specifications of how to connect these FPGA devices at a very high level. Then, we synthesize the pin assignment based on FPGA rules and how the chip will be placed and routed on the board. This is called 'route-aware'. "Automation enables a third thing that nobody has ever had: the architectural exploration," he further explained. "Because it takes minutes to do the pin-assignment synthesis, what users can do if they don't want to use large devices like a Virtex-6 or a Spartan-6 from Xilinx, they can go to a cheaper device and use more of those. They can do a real quick performance versus cost tradeoff. That tradeoff can be done in 2 to 3 hours depending on how many FPGAs you have. This would normally not be possible."



Hemant Shah further commented: "We worked a lot with customers to make sure the integration was seamless and, at the same time, with the FPGA vendors to make sure the designers can use the OrCAD and Allegro FPGA System Planner as a tool that brings the knowledge from the FPGA tools, all in one common environment so that all decisions are made not blindly but with knowledge and feedback from different domains. It brings three domains together and it has the intelligence to help the FPGA designers make the right decision with the automation behind it."

According to Vin Ratford, senior VP of marketing at Xilinx, the Taray FPGA I/O synthesis technology “can help designers integrate today’s high-capacity FPGAs into the PCB design process much more quickly compared to manual, error-prone methods for pin assignment and optimization”.


After a year or two of relative inactivity, FPGAs are only now moving into a new phase with the leading suppliers moving to 28nm process technology, which means even bigger FPGAs are on the horizon. And FPGAs have never looked as much like SoCs as they do in 2010 and that means complex I/O. "Taray's unique route-aware pin assignment synthesis technology has enabled us to get the fastest adoption of any new product we have introduced in the past 10 years," said AJ Incorvaia, VP of PCB engineering and IC Packaging at Cadence.



Clive Maxfield
reveals in his blog -
The guys and gals at Cadence say that the thing that finally spurred them to action (to acquire Taray) was the fact that – in the case of 7Circuits – they realized that they were seeing: "The fastest adoption of any new technology introduction in PCB Space at Cadence in the past 10 years." And why are users so excited? Well, consider a Qualcomm Case Study that involved using Taray's technology to create an FPGA-based prototype for an SoC. Previously, Qualcomm had implemented a 19-FPGA single-board system using traditional design techniques. Now, using Taray's technology, they created a 48-FPGA, five-board system in half the time! This means that – in the case of comparably-sized designs, you may expect to see an 80% reduction in design cycle time!

As always, feel free to express suggestions or ask questions about Allegro FPGA System Planner.

Jerry "GenPart" Grzenia


By TeamAllegro on March 26, 2010
EETimes Asia added a few extra nuggets - www.eetasia.com/ART_8800601697_480100_NT_b5b444b1.HTM

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