IBIS is sometimes known as the bird of knowledge, but is also the popular standard in modeling I/O buffers. Well, IBIS recently grew some big new wings when the 5.0 version of the spec was ratified. Those big wings include support for algorithmic modeling of SerDes transceivers. Instead of just modeling with numbers and tables, the 5.0 standard now allows software modules or dynamically linked libraries (DLLs) to be included in the model. This well defined software interface allows for very sophisticated algorithms that match the sophisticated equalization algorithms that take place inside the SerDes to be implemented by signal integrity simulation tools.
Official support for IBIS 5.0 AMI models is now available in Allegro PCB SI. While Cadence has supported the AMI standard for over two years, it was not until recently that the IBIS committee released their official parser and that has now been integrated into the latest PCB SI release.
Users of PCB SI should navigate to downloads.cadence.com, select SPB163 and download the latest hotfix.
Cadence is pleased that the work they first validated with IBM at DesignCon 2007 (see Interrogating the chips in 2007 EE Times article) has reached this ultimate level of standardization. It took a lot of time, energy, and cooperation with other companies, but both Cadence and Cadence customers will be well served for their patience and persistence.
After you have a chance to download the latest hotfix and work with our sample AMI models, please let us know your feelings about the “out-of-the-box” IBIS-AMI support in Cadence Allegro PCB SI.