As clock and data frequencies increase and high-speed systems become ever more densely populated, the distribution of power becomes a major challenge for package power/ground design. To ensure that high-speed systems continue to deliver the required performance at these new signal frequencies, power distribution impedance has to be controlled over a wider range of frequencies. This can be accomplished through careful consideration of the design of the switching power supply, bulk capacitance, ceramic capacitance and power/ground over the frequencies of interest. Having the ability to accurately simulate a power distribution system and synthesize the necessary quantities and values of decoupling capacitors is now crucial, as the power distribution system has become a critical element of system design in high-speed systems.
This feature provides a flow to analyze the power delivery for power nets in APSI and SiP SI. This flow uses Apache's PakSi-E 3-D field solver to model the power and ground nets of the package. You set the target impedance for given power net, then assign port types, group and excitation for die and package pins, and place various appropriate decoupling capacitors in the design. Then the equivalent circuit for simulation can be extracted.
The Package Power Integrity feature is available in the Allegro Package Designer SI L and the SiP Digital SI products.
Package PI also requires a third- party product, the Apache Paksi-E field solver. The PakSi-E solver is not licensed or provided by Cadence.
Tips and Workarounds
When the Paksi-E extractions fails, save the design, delete the paksi.run directory and restart the tool.
Package Power Delivery Analysis
In the Package PI solution, when you have board and on-die information, a complete analysis can be accomplished by using a subcircuit model for the PCB board as well as for the die. The equivalent circuit of the die and board can be extracted by either EDA tools or measurement. Both spice-like circuit and S-parameter models can be accepted. The PCB circuit model and VRM (Voltage Regulator Model ) do not need to be present for the tool to determine the "Z" as seen from the die. A more accurate impedance Z can be determined with more of the overall system modeled.
The PCB model which is now a 2 terminal subcircuit model and does not have to be present for analysis.
Step 1 — Preliminary Configuration
The following parameters are common for design and are out of the scope of the package PI flow, and should be configured correctly before analysis. In most cases, you should have set up these parameters correctly in package design editors, like the wirebond profile, bump and ball pins, and so on.
1. Identify power and ground nets' voltages and assign voltage property
2. Set up ball & bump parameters.
3. Set up bondwire profiles.
4. Set Paksi-E field solver parameters.
The Enable Multiport is typically YES and Frequency is the center frequency of the extracted model.
Step 2 — Power/Ground Net Information
1. Select a power net from the drop-down list.
2. Select ground nets for later decoupling capacitors' placement.
3. Set target impedance (voltage, tolerance, max ramp current and so on).
4. Select VRM model and board power supplier subcircuit. [Optional].
The Power Supply button brings up a form where the VRM model can be selected and edited. The form also allows you to select a subcircuit model for the PCB board if one is available. That PCB model is expected to come from measurement of a board, or some 3rd party extraction tool. A subcircuit model could be made with some assistance and effort by hand editing some files from an Allegro PCB PI board level simulation, but we do not currently have an automatic flow to use an Allegro board database.
The VRM model an equivalent circuit model consisting of an ideal voltage source and four passive elements. Many of the components are common to both a nonlinear and linear VRM. R0 is the value of the resistor between the VRM sense point and the actual load, and is usually only a few milli-Ohms. A VRM is not capable of regulating the voltage at the actual load.
L_out represents the output inductance of the VRM. It may be the inductance of cables that connect the VRM to a system board or it may be the inductance of pins that connect a VRM to a micro-processor module (about 200 nH and 4 nH, respectively). The maximum effective frequency for the VRM is determined by L_out.
R_flat represents the ESR of the VRM at frequencies beyond the response time of the loop. The ideal voltage source has the value of the power supply voltage. L_slew is the only element in the linear model that is not traceable back to an element in the nonlinear VRM model. The value of L_slew is chosen so that current will be ramped up in the linear model in about the same time as it is ramped up in the real VRM. It is calculated from the equation V=L(di/dt).
V is the amount of voltage droop or spike that can be accepted in the PDS (for example 5% of 1.8V). The maximum transient current is used for di. The total amount of time for the VRM to ramp this transient current either up or down is used for dt. The graphic shows a sample calculation for L_slew for a VRM that can ramp down 20 amps in 15 microseconds.
The VRM model can be text edited and so the internal subcircuit can be changed. PI will check the model to find out that this specified VRM model has only two terminal ports. If this model has only two ports, Package PI will view this model as a valid VRM model. It should be pointed out that you should be responsible for your own defined VRM model because a bad model for a VRM can cause a simulation failure that may not be easy to detect.
Step 3 — Port setup
There is a Port Information tab on the main Power Integrity form where die pads and BGA pins are setup and grouped together. The die current profile and circuit model are also set here.
All die and package components connected to the power net will be listed automatically and you should then configure the on-die information and port information.
1. Set die current profile [Optional].
2. Set on-die series capacitance and resistance, or subcircuit [Optional].
3. Set port group information for die and package components.
4. Set port sink/source type and sink excitation for die and package pins.
All package pins are forced to be SOURCE and you cannot change them. All die pins are considered to be SINK type by default. But you can change the die pins into OPEN or SOURCE type, because in some SiP cases, some die pins can act as sources.
Note: The actual difference between OPEN, SOURCE and SINK pins is that the current flowing through the SINK pins are pre-determined and fixed, while the current flowing through the SOURCE pins are variable and to be calculated, and no current flows through the OPEN pin. Tthe Paksi-E extracted subckt will not have ports for pins with an OPEN port type.
A whole column can be changed at once by using the RMB on a column header such as Port Type or Excitation. The port assignments can also be imported and exported to a file.
The ports are grouped into basic categories to use the multiport capability on the field solver. This makes a model of the package power and ground nets that have a connection for each port rather than the much larger connection for each BGA and DIE pin.
Consult the Paksi-E documentation for more information on port groups and multiport.
Step 4 — Decoupling Capacitor Selection and Placement
This is a repeating step for Power Integrity analysis until you get satisfactory simulation results.
1. Select an appropriate dml model for the decap. You can browse for the model from the design or import one from an Allegro part library, for example the power_integrity.dml or vendor supplied models. You can also edit the parameters on the models when necessary.
2. Place virtual decaps into the design.
Virtual decaps can be placed into the design with from the RMB menu on a Decoupling Capacitor. Place or move the pins on power and ground nets for best location to reduce the impedance profile. When they are verified as correct, you can replace them with instant decap, then finish fanout and routing for final analysis in APD or SiP.
Use the Visibility and Options to show each power and ground shape when placing the selected pin showing on the Options section.
The above figure shows pin 2 of a virtual capacitor on the GND layer on a shape associated with the VSS net with pin 1 already placed.
3. Add probe port in design for output [Optional].
Using the RMB out on the design canvas, you can add a probe port or VPort in the canvas to output the voltage ripple and impedance value on a specific point for testing purposes during the analysis. A probe port is a specific one-pin component that acts as an output port during circuit extraction.
Note: Both virtual decaps and probe ports are removed once Package PI exits and are restored when it is next invoked.
There are other virtual decap and Vport operations that can be done from this menu.
Step 5 — Extraction and Analysis
You can now perform the voltage ripple analysis in the time domain or target impedance analysis in frequency domain and check the result in SigWave. When the results doesn't meet the target, repeats steps 2, 3, and 4.
1. Select analysis type and options.
You can select the analysis type among voltage ripple analysis in the time domain, target impedance analysis in the frequency domain, or equivalent circuit extraction only. There is also an option to reuse pre-stored equivalent circuit extracted by the field solver in a previous analysis.
Paksi-E will automatically extract equivalent circuits for the selected power net and coupled ground nets, including bondwire, ball and bumping, vias, fanout of decoupling capacitors and so on, and store this in the Package PI working directory for later simulation. Paksi-E will extract the narrowband model by default, but you can change the parameter to extract another other type. Package PI uses the extracted model, builds the circuit with the extracted dml model, other dml models in virtual and instant decaps, VRMs, board and die power supply circuits, sink excitations and so on, and then pass it to TLSim for simulation. The netlist used for TLSim simulation is stored in Package PI working directory pdnAnalysis.run.
2. Check analysis results in SigWave.
After voltage ripple or impedance value analysis, Package PI displays the analysis results in SigWave. You can check the result with a preset target. Those points on the package where the impedance value or the voltage ripple exceeds the target at any frequency or time domain will receive particular attention and you can repeat step 4 to place the decoupling capacitors to achieve the target impedance.
SigWave displays the impedance at the different ports of the model. It also shows an Estimated Target Impedance which is calculated from the Voltage, Max Delta Current and Ripple Tolerance from the Power Integrity general form. There is also a display of the Calculated Target Impedance which is determined from the Excitation Sources on the current Sink ports.
Step 6 — Report & Export
You can view the detailed report for decoupling capacitors used in design for power integrity and export the decoupling capacitors used in design for the selected or all power nets. Use this report to guide the actual placement of capacitors on the package with APD or APSI
As always, please keep your suggestions and questions coming!
Jerry "GenPart" Grzenia