No - we're not talking teeth, candy, and cavities here ...
Many customers have been asking us to support cavities inside of the Cadence IC Packaging tools for a number of years now. These are most frequently requests from companies trying to design leadframe packages (a technology that Cadence does not support within either the APD or SiP toolsets), though some have come from customers wanting to embed a die within a regular BGA package substrate as well.
To implement a complete solution for cavity support would likely require significant engineering resources across multiple releases. There are many challenges to be faced and many commands to be updated. From making manual and auto routing understanding cavities to the complexities of modeling the cavity in signal integrity analysis and any fill material inside the cavity, the challenge can be daunting.
The aim of this feature is to provide a small first step in introducing cavity support, by allowing users to "push" a die stack into the surface of the substrate and down a specified distance or number of layers. For leadframe designs, where there is no package routing, this allows the user to get accurate analysis and 3D views of the design.
It is the intention to use this to open discussions for what is additionally needed to complete cavity support, but doing so in a manner that will allow for the logical extension into the complete solution without unnecessary changes to the use model or underlying data model inside the database.
I'll limit the details to defining the user interface and use model for cavity depth specification for die stacks. I'll not attempt to deal with problems such as preventing the auto-router or manual routing from trespassing inside the boundaries of the cavity on a given layer.
When setting up your die stacks after adding die components, spacers, and interposers to your design, you should ensure that the offset of the stack from the top/bottom of the substrate is accurately set. This will maximize the up-front accuracy of your database and any measurements, such as 3D bond wire lengths.
In order to mount a die stack within a cavity on the substrate, the user must launch the die stack editor command. On the main die stacks tab of the die stack editor form, select the appropriate die stack from the list. Then, select the layer atop which the stack should sit inside the substrate.
To view the impact of these changes on the design, launch the 3D Viewer tool. This will update to show the die sitting below the surface of the package substrate layers. Note that the edges of the cavity itself are not drawn in the 3D Viewer, as this tool only draws positive conductor objects, not negative region boundaries.
Graphical User Interface
The user interface for the die stack editor tool in SiP Layout and Architect has been modified to add new fields for specification of the depth of the stack relative to the surface it exists on. The new fields are defined below, and all exist on the "Die Stacks" tab of the form:
Sits on Layer: The user may select the layer on top of which the bottom of the die stack sits. For a surface-mounted stack, this is the outermost conductor layer of the design. All layers are listed in the pull-down, ordered relative to the stack’s substrate surface. Default value when changing to this method is the exposed substrate surface layer name.
If you have an applicable .sip file, we'll walk through an example. Open the design in 3D.
Notice that the bottom DIE is on the same layer as the power rings, the Surface Layer.
Open the Diestack Editor
You will NOT see the feature.
Close the Diestack Editor
In the command line type: set diestack_cavity_beta
Then open the Diestack editor once again and the feature will now be active.
Select Inner_1 for the Die to "Sit On".
Open the design once more in 3D.
The bottom DIE is now shown BELOW the surface layer.
Pan around to view this.
As always, I welcome your discussions on this new feature!
Jerry "GenPart" Grzenia