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What's Good About the new FPGA System Planner? - Ask Hemant Shah!

Comments(0)Filed under: PCB design, FPGA, FPGA System Planner, FSP

Our product marketing manager for Allegro PCB products, Hemant Shah introduced the FSP product in his Blog post - Innovative Approach to Optimized FPGA Pin Assignment

For an interesting interview about the new FPGA System Planner (FSP) product, please read the details here.

Here are some "take-aways" from Hemant's interview that I found noteworthy:

  • Our customers are leveraging the power, design flexibility, and cost savings of using FPGAs in designs in an ever increasing volume over the past few years. At the same time, to provide the increased complexity of designs, the pin count on FPGA devices is increasing - thus adding new design challenges for both the Electrical, and PCB Designers.
  • Pin assignments of the FPGA (to determine functionality) is usually a manual process and for large pin-count devices, this is cumbersome. Also, determining the optimal pin assignments to provide the best integration of the part on the PCB involves quite a bit of back-and-forth changes between the PCB Designer and FPGA Designer (and often without an automated method).
  • Some of the unique capabilities of FSP -

    • A relative placement of the FPGAs on the board can be controlled by the FPGA/Electrical Designer before sending the netlist to the PCB Designer. By optimizing this placement in advance, the routing solution is optimized.
    •  Pin assignments are automated using assignment rules during synthesis.
    • The FPGA Designer can do so much more pre-board planning, placement, and synthesis in advance of the schematic netlist driving the PCB. To quote Hemant in a nutshell - "The FPGA designer can do the placement, do the pin assignment, and take the results of the automated pin assignment to the FPGA vendor tools to make sure there are no issues with internal timing of the FPGAs. Once the FPGA designer is satisfied with the pin assignment and the internal timing of the device, that pin assignment can be sent over to the schematic process by exporting synthesized schematics that have the FPGA symbols and the connectivity that's associated with it. The hardware designer can then take that FPGA subsystem, integrate it with the rest of the PCB system, and pass it on to the PCB layout system."
    •  Because of the pin assignment rules built into the FPGA part libraries, the designers can catch incorrect pin assignments (wrong power voltages assigned on a multi-voltage design) using FSP. This is typically a manual process to "flag" these situations, but not with FSP.

As always, I welcome your comments and suggestions about the new FPGA System Planner product.

Jerry "GenPart" Grzenia


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