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Innovative Approach to Optimized FPGA Pin Assignment

Comments(4)Filed under: PCB design, FPGA, FPGA-PCB Co-Design

Cadence has been a leader in silicon-package and package-board co-design for over a decade now. Today, Cadence introduced a new and innovative solution for FPGA-PCB Co-design.

The FPGA-PCB co-design solution includes proven technology from Taray Inc for optimized, correct-by-construction FPGA I/O pin assignment synthesis that takes into account the placement and routing of the FPGAs.

What is unique about this technology is:

  • It provides automated FPGA I/O pin assignment that is accurate per FPGA vendors' pin assignment guidelines
  • It enables architecural exploration to do cost/performance trade-offs that is not practical with manual pin assignment methods.

To learn more about this exciting new approach, read more:

I would love to hear your comments, feedback on this new introduction from Cadence.


Hemant Shah


By Maxwell86 on May 19, 2009
Hi Hemant ... saw the chalk talk “FPGA-PCB Co-design done the right way”
techfocus.acrobat.com/cadence09042801  ... good stuff!

By Randy Dawson on June 2, 2009
We are struggling with high pin count devices and pin/gate swapping and the possibility of tools like this to address the problem.  Its not an FPGA, it is a 2k pin count connector set for a semiconductor tester (example - LTX)
I'm wondering if anybody has used a FPGA tool to handle the I/O mapping in an application like this.  We have similar I/O rules, like banks of diff pairs, analog channels, power pins etc and we need a way to manage these in a schematic and optimize the routing.  

By Hemant Shah on June 5, 2009
Hi Randy,
I believe we may be able to help you with your challenge. Would you like to connect up with me offline?
My email is shah@cadence.com

By Maxwell86 on June 11, 2009
Hi Hemant,

I also saw your interview in PCBDesign 007 ... www.pcbdesign007.com/.../zone.cgi ... more good information ... thanks!

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