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Designing DDR3 Interfaces In a Constraint Driven Design Environment

Comments(1)Filed under: PCB Signal and power integrity, DDR3, Constraint Manager, SPB 16.2

If you’ve been wondering how to capture high speed memory interface design intent early in your design process and drive that through to final verification, the Allegro PCB team has a number of ways we can help.

First, be sure to attend or watch a recording of the webinar planned for March 11 where we will walk through some of the latest technology built to address high speed memory interface design.  You can register on this page.

After the webinar, you may want to look into our web-based, self-paced training courses.  To learn more, watch this video as Dave Palumbo of our Educational Services team introduces you to a course that teaches the front-to-back constraint managed flow using a DDR2 memory interface as an example.

Registering for a course or to see the full catalog of training courses can be done at www.cadence.com/education

Let us know what you think of the webinar and / or  the training course.

 

Comments(1)

By Kishore on April 7, 2009
Designing DDR3 Interfaces In a Constraint Driven Design Environment

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