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What's Good About FPGA Capabilities in Capture? Download the SPB16.2 Release and See!

Comments(5)Filed under: PCB design, Allegro, SPB 16.2, UCF, FPGA: PCB, xilinx

With the SPB16.2 release, a few new FPGA enhancements have been added.

In recent years, the design of FPGA and Printed Circuit Boards (PCBs) has become increasingly parallelized as opposed to the traditional sequential model.

The basic symbol information such as pin name and pin number may be gathered from multiple sources. For instance, symbol information can be copied and pasted from the device user guide. This is not recommended since it is easy to mistakenly copy the wrong information or omit some pins. A more common way if you have a placed and routed FPGA design, is to generate the I/O file, called a PAD file, from within Xilinx ISE (.pin file in Altera). This PAD file contains all the specific I/O information like Pin Number, Signal Name, Pin Usage, Pin Name, Direction, IO Standard, IO Bank Number, etc. about your particular design. A PAD file requires an implemented FPGA design which you may not already have especially if the PCB and FPGA design processes are highly parallelized. In such cases you can use the CSV output from an I/O assignment done in PACE or the Floorplan Editor of ISE Xilinx.

Earlier, Capture CIS was only capable of generating a single section part when PCB designer uses the .pad or pin files to generate a part. In the 16.2 version, Generate Part has been enhanced such that PCB designer can generate a part based on the information like IO Banks/IO Standards/power pins in one section, pins visibility in a very easy and efficient manner.

There are several occasions throughout the design process where pinout changes may happen in the schematic tool and must then be propagated to the FPGA user constraint file (UCF). For instance, the board design may have started before the FPGA internal logic. Therefore, pins may have been added, removed, renamed, or relocated. The schematic engineer may also discover improperly assigned pins or that the system specifications have changed requiring more, fewer, or different I/O properties. The Xilinx ISE user constraint file (UCF) must be kept in sync with the board I/O to avoid a system malfunction. You can make a swapped pin symbol and create a .ucf file during the Export FPGA.

As always, I look forward to your suggestions about these new enhancements.

Jerry GenPart

Comments(5)

By ten vn Q227 on February 23, 2009
I would like to download the OrCAD 16.2 Demo Software. Please help. Thank you

By Jerry GenPart on February 23, 2009
Hi ten vn Q227. There's no "demo" software per se. You can obtain an evaluation copy of the OrCad software by contacting your Cadence Sales Representative in your geography. Please contact him or her for details.

By JimG on February 24, 2009
Jerry it's good to see your still around and doing well ? It's Jim from USR. Later.

By Jerry GenPart on February 24, 2009
Hi Jim! Glad to see you're still using the Cadence tools! For those who may not know - Jim is a long time Allegro customer who has provided numerous product suggestions with some becoming new features in the product. He's an expert with out products. I'll send you a private Email Jim so we can "catch-up". Jerry

By Ejlersen on February 25, 2009
Hi, The OrCAD 16.2 Demo Software can be downloaded from now. Lool at www.cadence.com/.../downloads.aspx. Best regards, Ole

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