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What's Good About Advanced Plating Bar Checks - Check out the SPB16.2 Release and See!

Comments(1)Filed under: PCB design, Allegro, SPB 16.2, advanced plating bar check, advanced package designer, BGA

New functionality has been added to the SPB16.2 Allegro Advanced Package Designer (APD) suite of tools to support Advanced Plating Bar Checks.

The plating bar check command has existed inside of the APD and SiP tools for many years. However, as the design of IC packages has continued to evolve, the needs for this command continue to change. As an example, in the past, it was necessary only to check that the balls of the package (BGA) be checked for connectivity, and optionally the bond fingers for a wirebond die. Now, discrete components are being embedded into the design, etch-back techniques are being used to plate dense designs, and multi-chip packages contain nets which are completely internal to the package, having no connection to the BGA component pins.

While much of this functionality is simply added on to the existing plating bar command (being a much-used utility in the packaging tools, changes to the command are not made without care), some impact to the current workings will be inevitable. As a result, it will be more useful to describe the command as a whole, rather than just the additions and modifications.

Use Model

While the use model for this command is unchanged from past releases, we will go through it briefly, here.

Essentially, once your design is routed, at least partially, you can create a plating bar. From that point on, you can run the plating bar check whenever desired to get an up to the minute report on any nets which are currently not plated in your design.

This can have an impact on how you proceed with the design, in terms of the number of required routing layers versus using etch-back processing to create temporary shorts for plating purposes, etc.

Basically, launch the command, configure the form, and press “OK”. At this point, it becomes a batch process based on the form configuration and reports results in the form of external DRC markers in the drawing and a log file, described later in this document.

 

Menu and Command-Line Access

     Menu Pick: Manufacture > Plating Bar Check

     Command Line: pbar check

Graphical User Interface

The interface for this tool is shown in the figure below.

The fields are defined as follows:

·        Check for unplated nets: This option controls all the fields below it on the form, and governs the plating checks relating to actual (logical/physical) connections to the plating bar. It defaults to on.

·        For multi-pin nets, check all: These fields (described in detail below) apply to nets which have more than one item to be plated. As an example, a net from a wirebond die to a bond finger, out to a BGA ball, has two items to be plated (the ball and finger). If a specific item type from this group is disabled, as soon as any item (of any type) from the net is plated, all objects of that type are plated. To continue the example, if we turn off BGA balls as an option, and the bond finger is properly plated, then the BGA ball, if unplated, will not report an error.

·        BGA balls: Check BGA balls (IO class components) in the design for plating connections. This defaults to on.

·        Bond fingers: Check bond fingers in the design for plating connections. Wirebond die pads are not checked directly. Only bond fingers are checked, as there is no way besides a bond wire to connect a wirebond die pad down to the substrate surface. This defaults to on.

·        Flip-Chip pads: Check all pins of flip-chip die components for plating connections. This is a new option in this release and will default to on. To restore original behaviour, disable this option.

·        Discrete component pins: Check discrete component pads for plating connections. This is a new option in this release and will default to on. To restore original behaviour, disable this option.

·        Allow indirect connections through other components: The plating bar check does not, by default, consider connections through other component pins to be a ‘legal’ (advisable?) means of plating. For example, a BGA ball which connects to a bond finger, which then connects to a different ball and out to the plating bar would not be considered plated. To change this behaviour, select this option. The default is off.

·        Perform etch-back plating checks: Off by default, this option will cause the tool to check any nets not directly connected to the plating bar for connections through an etch-back trace. The performance of this check can be slow, so if there is no etch-back in your design, it should be left disabled.

·        Report dummy net violations as errors: By default, dummy net pins will report only as warnings by the plating bar check. Since these pins are not currently in use, their plating is not required. Some design flows require even dummy nets to be plated (most likely in case the pin becomes used in a later iteration of this substrate). In these scenarios, this option should be enabled. It is off by default.

·        Highlight unplated nets (dehighlights plated nets): If enabled, unplated nets will be highlighted in the design after the plating bar check is run. As noted, nets that ARE plated will be dehighlighted. This defaults to off, to preserve the design colouring set by the user.

·        Color: Pull-down colour selection to use when highlighting the unplated nets. This defaults to the first colour in the pull down.

·        Check for plating trace space violations: This checkbox will enable all the fields in the column below it. Spacing violations measure the clearances between neighbouring plating bar traces to see if they are likely to cause manufacturing problems when the plating bar is removed during the late stages of manufacturing. This defaults to on.

·        Min separation: This value specifies the minimum separation distance (as measured between the clines where they meet the plating bar itself) between two plating traces on the same layers. This is used to ensure that, when the plating bar is removed, extra metal from one plating trace doesn’t bend down and short against the other. The default value is the line-line spacing constraint value on the bottom conductor layer.

·        Edge distance: This modifies the minimum separation constraint. If the value is non-zero, minimum separation is checked this distance in from the plating bar boundary. The default value is 0 to maintain existing functionality, which implies separation is measured at the plating bar edge only.

·        Min offset: This value specifies the minimum separation distance (as measured between the clines where they meet the plating bar itself) between two plating traces on adjacent layers. This is used to ensure that, when the plating bar is removed, extra metal from one plating trace doesn’t bend down and short against the other. The default value is ½ the line-line spacing constraint value on the bottom conductor layer.

·        Min length: This specifies the minimum length of the final, straight-line segment going to the plating bar pin. The purpose here is to ensure that the cline will not get sheared off at an angle when the plating bar is removed. This defaults to 0.00, which implies everything is alright, and maintains existing behaviour.

·        Clear DRCs: Clear all plating bar related DRCs from the design.

·        OK: Exit from command, after running plating bar check to update the design based on the current form config.

·        Close: Exit from command without running plating bar check.

       Help: Invoke context-sensitive entry for this command.

 

 Log File and Contents

A sample log file is provided below. Essentially, the following messages are possible (the actual values for pin/net/finger names, locations, and required/actual values will change per design content):

ERROR:   Minimum plating trace spacing violated (Required: 5 UM; Actual: 4 UM)
         At (0.000 0.0000) (Net “ABC” and Net “XYX”).
ERROR:   Minimum plating trace straight line length (Required: 5 UM; Actual: 4 UM)
         At (0.000 0.0000) (Net “ABC” and Net “XYX”).
ERROR:   Minimum plating trace offset violated (Required: 5 UM; Actual: 4 UM)
         At (0.000 0.0000) (Net “ABC” and Net “XYX”).
ERROR:   BGA.A1 not connected to plating bar WARNING: BGA.A2 not connected to plating bar WARNING: BF23 is plated through an etchback connection WARNING: U1.45 has multiple (4) connections to plating bar

ERROR:   No plating bar component found.
         Likely cause: plating bar has wrong component class.

Jerry Genpart

Comments(1)

By wangjun on November 30, 2008
good enough.

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