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Techtorials, Demos, Roadmaps ... Poker?

Comments(0)Filed under: Front-end PCB design, AMS simulation, PCB Layout and routing, PCB Signal and power integrity, Library and design data management, PCB design, SPB, Design Entry HDL, Allegro System Architect (ASA), Differential Pair Support, ASA, ConceptHDL, DEHDL, Capture CIS, SPB16.01, Allegro PCB Editor, OrCAD Capture, OrCAD PCB Editor, High-Density Interconnect, HDI, CDNLive

What do these 4 have in common? CDNLive! 2008 San Jose - September 8 - 11, 2008. This is an outstanding event where we can learn about how companies are using Cadence solutions to expand their design environments. While most customers attend this event to learn all the new and exciting capabilities of SPB solutions through the customer and Cadence papers/presentations, there are a host of valuable events that are available:

    • On Monday, you'll have the opportunity to participate in several highly technical sessions that will increase your productivity in using the SPB16.2 features.
    • Sessions you can select include -
      • "What's New in PCB 16.2" - You'll learn the details about the productivity and ease of use improvements made to the Allegro PCB Editor for PCBs that use High Density Interconnect for build-up technology. Topics included are Improvements to Design Partitioning, Placement application mode and replication, Snapping, Differential Pair support by region, and Graphics enhancements.
      • "What's New in IC Packaging/SiP Layout" - You'll lean how the new Allegro HDI capabilities can result in a greater design miniaturization, the new IC package/SiP design partitioning, the new DFM-driven features, and the new SiP co-design capabilities.
      • "SI - Serial Interface" - You'll learn how the new technology in Allegro PCB SI enables fast and accurate modeling and simulation of transceivers and interconnect. In addition, you'll see how the new technology can be used to efficiently validate bit error rate (BER) requirements.

    • See these detailed demonstrations Tuesday evening:
      • Design Entry - HDL Is Easy to Use!
      • Designing Probe Cards Using Allegro System Architect
      • The Latest Virtuoso-Driven SiP RF Flow
      • Latest Allegro Package Designer/SiP Layout Editor Features

    • On Wednesday, attend the Roadmap presentations and ask the Cadence experts at the Technology Panels
      • PCB and IC Packaging Roadmap
      • Allegro Platform Technology Panel: Ask the Experts!
        • The Allegro platform Technology Panel provides an open forum for YOU to ask questions of the product development team experts on everything from basic tool issues to roadmap items. This is your chance to go directly to the experts who drive product direction and engineer the solution.

Of course, there will be relaxing periods as well to network with friends in the industry, speak directly to Cadence R&D, Marketing, and Application Engineers, and join the Celebration of Cadence's 20 years event Tuesday evening.

And what about that last item - Poker? On Wednesday morning, you'll have the opportunity to hear from Phil Gordon a Professional Poker Player / Analyst. In the evening, you can participate in the Texas Hold’em Poker Tournament!

 Let me know if you'll be attending - I look forward to seeing all those customers I work with every day in Customer Support!

Jerry GenPart

P.S. I'll be presenting a paper - "Allegro® Design Entry HDL – User Customizations" on Tuesday morning and I look forward to your questions and suggestions during the "Canvas Conversations" event that afternoon.

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