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IC6.1.6 Virtuoso Space-Based Mixed-Signal Router (VSR)

Comments(0)Filed under: tech-on-tour, mixed-signal ToT, Tech on Tour, open access, OA: OpenAccess, Technology on Tour, analog/mixed-signal, MS ToT, mixed-signal training, Router, VSR

Virtuoso Space-Based Router (VSR) is routing solution integrated into the Virtuoso Layout Suite, which provides a comprehensive set of routing features for a variety of layout tasks. One major design task for layout designs is chip/block assembly routing in mixed-signal analog top (AoT) designs.

What's new in Virtuoso IC6.1.6?

VSR routing engines were enhanced to improve routing quality (QoR) and to give better control over routing flow. You can run automatic routing using the Wire Assistant for improved usability. Now most of the functionality found in the Route --> Automatic Routing UI can be found on the enhanced Wire Assistant.

One of the benefits of using the Wire Assistant is that settings are consistent across all use models (Interactive Wire Editor, assisted routing, or automatic routing). Using the new Wire Assistant, users have control over pin access, via configuration, routing flow, and routing style/topology. Regarding topologies, the Wire Assistant adds support for these routing topologies:

In addition, the Wire Assistant has three pre-defined routing flows:

As in IC6.1.5, the Wire Assistant will dynamically populate sections in the UI to control any specific routing features.

Which technology nodes are supported?

VSR in Virtuoso IC6.1.6 supports design rules (constraints) for a broad range of technologies, from very mature "analog" nodes such as 0.25µm and 0.18µm, all the way to 22nm.  In Virtuoso ICADV12.1, VSR supports advance routing rules for 20nm and below technologies, with support for double patterning (DPT) rules and interactive coloring.

If I need to add constraint, which routing constraints are supported?

VSR, as part of the VLS constraint-driven environment, supports specialty routing constraints such as bus, differential pairs, match length, symmetry, and shielding, as well as netClass and process-rule overrides (PROs, also known as non-default rules (NDRs)) for custom width and space and multi-cut via. It is also good to know that routing constraints are stored in OA, which makes them fully interpretable with EDI. So all routing constraints can be defined and edited in either VCM or in the EDI Constraints Editor to be used by the appropriate tools.

In my design, some of the macros have the abstract view and some do not. Do I have to generate abstracts for all my macro blocks?

No, but...  Using some form of abstract will help to improve routing performance.

In order to simplify the use model, "Cover Obstructions" can be used for "on-the-fly" abstraction of macros (Cover Obstructions requires all pins to be placed on the prBoundary edge of the macro block).  To use Cover Obstructions, go to Tools --> Cover Obstruction Manager.

When detailed abstracts are needed, as in cases when the use of the Abstract Generator is recommended for the control of routing porosity. To invoke, type "abstract" at the same location Virtuoso was invoked from.

What are the requirements for using VSR?

There are few things one should consider when using VSR automatic routing: The "cleaner" the layout data is, the easier it is for VSR to complete its tasks, which translates to higher quality of routing and better performance.

Here are few data requirements that should be checked prior to running automatic routing:

  • Technology File - Apart from routing layers and via definitions, there should be at least three constraints groups defined:
    • Foundry - Defines design rules (constraints) for layers such as minWidth and minSpacing
    • VirtuosoDefaultSetup - Most often is the default CG. Defines valid layers and vias for routing
    • VirtuosoDefaultExtractorSetup - Most often the default CG for VLS XL in order to extract connectivity
  • Connectivity - It must be extracted, as without connectivity VSR will not be able to run. Therefore, use VLS XL to establish a clean connectivity
  • Pins - Make sure there are no blocked pins and that pin sizes, locations, and spacing are legal. Best practice is to make sure the pin layers will adhere to the layer routing directions
  • prBoundary - Make sure all top level blocks (macros) have a prBoundary object at their top level
  • Layers - Setup valid routing layers, valid vias, and layer direction
  • Constraints - Specialty routing (DiffPair, bus, etc.) are better routed first. Use netClass constraints to define width, spacing, minimum number of via cuts to a set of nets

Why should I care about the signal type?

In IC6.1, unless specified otherwise, all nets are generated as type "Signal" and by default, VSR will route all nets of this type (Signal).

In order to differentiate the power and ground nets and force VSR to skip these nets during the automatic routing flow, users should specifically define these net types. To define nets to be of type Power or Ground:

  1. Use the Navigator to Search and Select all power or ground nets
  2. Use the Property Editor to change Signal Type to Power or Ground for the selected set of nets

Ready to route?

To route all nets, click the "All" button on the Wire Assistant "Automatic" section.

Or, select nets on the Navigator and click "Selected" on the Wire Assistant "Automatic" section to route only the selected set of nets.

Want to see VSR in action?

Navigate to support.cadence.com, look for Resources - Rapid Adoption Kits - Virtuoso Custom IC and Signoff and download a tarball to try out the new VSR or contact your Cadence account team for a live demo.


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