If you're a fan of the Star Trek series (my
six-year-old son and I watch it together faithfully!), you know the Vulcan Mind
Meld. (If you're not a Trekkie, the mind-meld is a process of transferring
one's knowledge to another person instantly).
Mixed-Signal Technology Summit, Oct. 10 at Cadence's San Jose campus, is
the closest thing to a mind meld to share mixed-signal design practices and
challenges among the design community. We've gathered members of academia, industry
visionaries and the mixed-signal design experts for an event packed with
technical insights and excellent for networking.
For this year's summit, we have
Professor Terri S. Fiez from Oregon
State to talk about 'Challenges in Emerging Mixed-Signal Systems and
Applications,' Geoff Lees, Senior
Vice President and General Manager Microcontrollers at Freescale, to talk about
Internet of Things and related business opportunity and applications. The academic and industry keynotes will
provide a good balance to what is current and what might be the challenges
for the future.
Here are some topical highlights:
- On the mixed-signal
methodology front, Cadence's customers are leading the way to talk about
the verification challenges/solution and implementation challenges/solutions targeted for bringing complex mixed-signal designs to the market.
- On the verification front,
Cirrus Logic and Cadence will introduce Digital verification methodology using
Real Number Models focused on the latest IEEE 1800-2012 SV-DC
standard (SV-RNM). Brian Fuller, my colleague at Cadence, has written an
excellent blog on this topic.
- On the implementation front,
ST Microelectronics, MicroSemi and Rambus will talk about the latest advancements
in the Cadence Virtuoso platform to enable seamless mixed-signal implementation
- On the cores front, we have Cadence's IP team to talk on the Cadence's latest
portfolio that is available for customers.
Below is the agenda for the Oct. 10 Mixed-Signal Technology Summit.
Attendees will receive a free copy of the Mixed-Signal Methodology Guide and can participate in a raffle drawing to win a GoPro camera
or a Kindle.
If you are interested and want to participate,
click on the link here to register. I look forward
to meeting everyone at the summit.
- 8:30-9:30 a.m.: Registration and Breakfast
- 9:30-9:45 a.m.: Welcome
and Opening Remarks by Dr. Chi-Ping Hsu, Sr. VP R&D and Chief Strategy
- 9:45-10:30 a.m.: Academic
Keynote: Challenges in Emerging Mixed-Signal Systems and Applications by Prof.
Terri S. Fiez, Professor & Head EECS Dept, Oregon State University
10:30-11:15 a.m.: Industry
Keynote by Geoff Lees, Senior Vice President and General Manager
11:15-11:30 a.m.: Break
11:30-12:00 p.m.: Mixed-Signal Trends-Foundry View by Douglas Pattullo, Technical Director, TSMC
12:00-12:30 p.m.: Mixed-Signal
Solutions Update by Koorosh Nazifi, Group Director, Initiatives R&D,
12:30-1:30 p.m.: Lunch with
- 1:30-2:00 p.m.: Mixed-Signal Verification Methodology using Real Number Models by Tim
Pylant (Cadence) & Bhupi Manola (Cirrus Logic)
- 2:00-2:30 p.m.: Methodology for Verifying SerDes Bit-Error-Rate Using Real Number Modeling by
Michael Hufford, Staff Design Engineer, Cadence
- 2:30-3:00 p.m.: Cadence-Mixed-signal Implementation Update by Steven Lewis, Product Marketing
Director, Analog/Custom Marketing, Cadence
- 3:00-3:30 p.m.: Virtuoso
Mixed-signal "Smart Power" Implementation Flow (case study) by Livio
Fratantonio, ST Microelectronics
- 3:30-3:45 p.m.: Break
- 3:45-4:15 p.m.: Micro-Semi: OA Based Netlist on Top Flow (Case Study) by John M. Williams,
Director of CAD Engineering, Microsemi IC Group, Microsemi
- 4:15-4:45 p.m.: Interoperable Database for Mixed-Signal Designs Netlisting by Mark Snowden, CAD
- 4:45-5:15 p.m.: Mixed-Signal IP Offerings by Cadence IP Team
- 5:15-5:20 p.m.: Concluding
Remarks & Raffle Drawing
- 5:20-6:30 p.m.: Social
Hour and Networking
Mixed-Signal SoC Verification, Say Good-bye to the Black Box Problem
--Mixed-Signal Methodology Guide