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Mixed-Signal -- Successful Tech-on-Tours, Huge Focus at DAC 2013

Comments(0)Filed under: mixed-signal, mixed signal, CPF, wreal, Virtuoso, AMS Designer, real number modeling, verification, Schematic Model Generator, Internet of Things, amsDmvmv, Conformal Low power, SMG, PIEA, ARM Cortex-M, DAC 2013, CLP, MDV, Mobile

We just completed some hugely successful Mixed-Signal Tech-on-Tours in North America. I am back in San Jose after this whirlwind trip that covered 9 cities in 4 weeks. Even though being on the road does get tedious, what kept me excited was the enthusiasm shown among Cadence customers for the Mixed-Signal Tech-on-Tour events. Close to 400 customers attended these Mixed-Signal Tech-On-Tour events.

The Dallas Mixed-Signal event in particular highlighted the interest among Cadence customers to learn about the latest Cadence mixed-signal verification methodologies. The original venue had a fire accident in the morning and we were forced to move the event to a hotel a few miles away. To my surprise all of the attendees came to the new venue and stayed for the entire event. I would like to salute the Dallas attendees for their patience and passion.

As you know, the key market drivers for mixed-signal designs are as follows:

o    The explosive growth in mobile applications mainly due to smartphones and tablets. This requires highly integrated Analog/Digital/RF designs and Increased frequency and speed for broadband demand.

o    Power management requirements across the entire spectrum of design applications, which includes mobile and data centers that need to minimize energy consumption.

o    The Internet of Things phenomenon that has led to MCUs being embedded in most of the devices and to digitally assisted analog designs.

The following chart shows the biggest mixed-signal methodology challenges as identified by Tech-on-Tour attendees.


Mixed-Signal methodology challenges (data based on worldwide survey of 561 Mixed-Signal Tech-on-Tour attendees)

As you can see from the above chart, mixed-signal verification remains the key challenge facing today's mixed-signal designers. Here's a deeper look at challenges and solutions.

o     The inherently long run times of the analog SPICE solver have led to a bottleneck in verifying mixed-signal designs. Analog behavioral modeling has been gaining traction for SoC level functional verification. At Cadence we have introduced Virtuoso mixed-signal behavioral modeling technology that includes Schematic Model Generation (SMG) and AMS Design & Model Validator (amsDmv) to assist in the creation and validation of analog behavioral models. With Real Number Models (RNM), analog behavior is captured in model that can be used in an event driven digital simulator to speed up SoC level verification.

o    The increasing importance of power management has led to the use of complex low power techniques in the analog portion of mixed-signal designs. This has led to the verification of power intent as the key challenge in these low power mixed-signal designs. With the CPF based Virtuoso AMS-Designer flow, users can now run dynamic low power simulation to verify the power intent. For static low power verification, Cadence has introduced the Virtuoso Power Intent Export Assistant (PIEA) in Virtuoso-XL that can used to create the CPF macro-model for the analog portion of the design. With the CPF macro model, Conformal Low Power can be used for static low power verification.

Low-power structural check flow using Virtuoso PIEA and Conformal Low Power

At the Design Automation Conference (DAC 2013) June 3-6, you can learn about Cadence mixed-signal solutions at the Cadence Suite sessions. Sessions include "Low Power Verification of Mixed-Signal Designs" in Suite 1 at Monday 1pm, and "Mixed-Signal Verification"  in Suite 1 at Wednesday 11am.

In addition to the suite demo session in the Cadence Suite, we have a dedicated Mixed-Signal/Low Power Pods staffed by Cadence's Mixed-Signal experts. The demo pods are located at the Cadence Booth and the ARM Partner booth. The Pod Demo showcases Cadence's comprehensive low power mixed-signal solutions based on an ARM Cortex-M based Fuel Chamber pressure regulation system.  In the pod we cover both implementation and verification targeted at MCU-based mixed-signal designs.  We also have key R&D experts available at the Cadence booth to cater to Cadence customers.

I am very excited to bring Cadence Mixed Signal solutions to the customers at DAC. I hope to meet you all at Austin next week.

Sathishkumar Balasubramanian











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