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"Smart Devices" and How They Affect Your Mixed-Signal SOC Verification

Comments(1)Filed under: analog, mixed-signal, mixed signal, Verilog-AMS, wreal, Virtuoso, AMS, RNM, mixed-signal verification, Virtuoso environment, analog/mixed-signal, analog behavioral models, DVCon 2013, Verilog AMS, SV-DC, Schematic Model Generator, Incisive, Internet of Things, CDNLive 2013, smart devices, SenseAware

We are seeing a huge trend -- the mobile revolution is changing the way we go about our everyday lives. Gone are the days where the term 'Internet'  was associated with a PC or Mac. The smartphone revolution has changed how  the data is consumed and used by consumers and businesses. For example, with the new line of smart systems, every device or appliance is connected to the Internet to manage their services in a better way with users and other connected devices.

A good example in a B2B segment is the new  "SenseAware" device by FedEx. These devices are used by FedEx for individual  tracking of packages. The SenseAware devices are compact and power efficient. These devices monitor location, temperature, humidity and air pressure, and communicate in real time to the Internet. The information is accessible to authorized users.  Thus, "Internet of Things" is a catchy phrase that has started to play a major influence in making human lives much more productive, easy and profitable.

These smart devices have started taking over the majority of the electronics markets by volume. It is predicted that we will have close to 20 billion of these devices by 2020. Smart devices are predominantly mixed-signal SoCs with analog and digital components on the same die. The key challenge that faces these complex mixed-signal SoCs is in the top level functional verification. This challenge is mainly attributed  to the simulation bottleneck that plagues these complex mixed-signal SoCs.

Both the analog and digital simulators have to be run for SoC verification.  The complex analog to digital and digital to analog interactions have to be properly accounted for and verified with acceptable coverage levels. However, with the traditional black box approach, there are more chances for functional failures that can result in costly re-spins and result in time to market delays that can be very detrimental to profitability.

To address these verification challenges for mixed-signal SoCs, Cadence offers a complete set of mixed-signal verification solutions for analog-centric as well as digital-centric users. Analog-centric users have successfully been using the Virtuoso AMS Designer solution to apply mixed-signal verification test benches to both transistor-level and AMS behavioral views of cells and subsystems. For the digital-centric users, Cadence has also been successfully enabling customers to adopt discrete real number models (RNM) of analog blocks to allow ultra high-speed verification of mixed-signal SoCs. The key is for designers to recognize the need for their analog and digital teams to work together in both the modeling and verification arenas. It's the only way they can seamlessly verify the operation of their entire mixed-signal SoC.

Real number modeling is a signal-flow based approach that uses real (floating-point, continuous) values to represent current or voltage in discrete time. The most obvious advantage of using RNM for top-level SoC verification is that it runs nearly as fast as pure digital simulation in fast digital simulators such as Cadence's Incisive Enterprise Simulator, which is many times faster than SPICE-based simulation or even analog behavioral modeling. This makes full-chip verification possible for large mixed-signal SoCs. Digital simulation speeds permit nightly, high-volume regression tests. With no analog engines, there are no concerns about convergence errors. In addition to allowing digital simulation speeds, RNM lets designers use digital verification techniques such as assertions, coverage, and metric-driven verification as part of their overall mixed signal SoC verification effort.

Many languages support RNM including Verilog, SystemVerilog, VHDL, e, and Verilog-AMS. Wreal is a native Verilog-AMS language feature that brings the benefits of digital signals into Verilog-AMS. For example, wreal allows real variables on ports. Cadence has developed a Verilog-AMS based RNM solution for customers looking for high performance and reasonably accurate modeling of analog behavior to aid verification of mixed-signal designs. This was implemented using the Verilog-AMS language features while extending them to improve the effectiveness of wreal signals as a way to model analog behavior and signal interactions.  

RNM is not, however, a replacement for analog simulation. It is not appropriate for low-level interactions involving continuous-time feedback or low-level RC-coupling effects. Nor is it intended for systems that are highly sensitive to nonlinear input/ output impedance interactions. And, real-to-electrical conversions require some careful consideration. If one is too conservative, there will be a large number of time points. If one is too liberal, there can be a loss of signal accuracy. With the recent introduction of the Cadence Virtuoso Schematic Model Generator for behavioral model generation and Virtuoso AMS Design and Model Validator Cadence is helping designers to extend metric driven verification to the Mixed-Signal world.

If you are interested in learning more about RNM and next generation mixed-signal verification technologies there are several opportunities to interact with Cadence mxed-sgnal verification experts in the next few weeks. At DVCon 2013, you can visit the Cadence booth or participate in various sessions. There is also a dedicated  mixed-signal track at CDNLive Silicon Valley in March. It includes sessions that focus on addressing mixed-signal verification challenges using  Cadence mixed-signal verification solutions. Finally, the recently released Mixed-Signal Methodology Guide available from Cadence is an excellent resource.

Sathishkumar Balasubramanian

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