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Tech-On-Tour: Bringing Advanced Mixed-Signal Design Methodology from Concepts to Reality

Comments(1)Filed under: mixed-signal, mixed signal, CPF, tech-on-tour, Tech on Tour, OpenAccess, Virtuoso, Encounter, mixed-signal methodology, DAC, Technology on Tour, Incyte, Cortex-M0, Mixed-Signal Methodology Book

About a year ago, Cadence offered a worldwide Tech-On-Tour (ToT) series for mixed-signal designs. One main objective of this seminar series is to bring the awareness of the need for a design methodology change to the broad mixed-signal designer community worldwide. The event was very successful and you can find some previous blog coverage here:


M/S Technology on Tour Blog - Model Validation and Assertion Based Verification

Is China Ready for Next Generation Mixed-signal Design?

Analog/Mixed-Signal Behavioral Modeling - When to Use What

Recently, Cadenced announced a new series of worldwide Mixed-Signal ToT events. What’s new this time compared to what we delivered one year ago? One major shift in this new series is that we will focus more on how to deploy the new methodologies into real designs, rather than the methodology itself. Many of the methodologies we had been promoting over the past a few years have become more and more mature with support from EDA tools in production.

In fact, Cadence recently announced the pending availability of a Mixed-Signal Methodology Guide later this summer and showcased the preproduction copies at DAC 2012. To demonstrate that some of the mentioned methodologies are ready for deployment for production designs, we will include four tool demos in this seminar. Depending on the availability of R&D presenters and regional requirements, some or all of the following demos will be shown:

  • Mixed-signal low power verification demo: CPF aware mixed-signal simulation for designs with power management features, automatic CPF macro model generation for custom or mixed-signal blocks, and application of formal methods for SoC low-power verification.
  • ARM Cortex M0 demo: Mixed-signal simulation of a Cortex M0 based fuel tank pressure control system using Verilog-A and wreal models for analog components with software debugging capabilities.
  • Architecture level design exploration demo: Using Cadence Incyte Chip Estimator to explore different IPs in a mixed-signal design to make architectural level decisions for best PPA tradeoff.
  • Mixed-signal implementation using OpenAccess based interoperability demo: OA based interoperability between Virtuoso and Encounter to enable an integrated physical implementation flow for analog centric mixed-signal designs.

The Mixed-signal ToT starts with a seminar in Taiwan on June 21 and will be expanded to many other different regions worldwide throughout the rest of the year. If you are interested in having the event in your region, please send your request to

Qi Wang 


    By CZ Chen on July 1, 2012
    The concept of "schematic-driven" or "netlist-driven" and "parallel Virtuoso-Encounter implementation for fast design closure" were introduced in China in 2011. Who are the fast leaners? Many global engineers in China, TI, NXP, IBM, FSL and many others always pick up shortly after; while more local engineers have begun to pick-up and to adopt in their designs. What are new? MDV-CPF? ARM-CM0?  InCyte? and OA update? We'll continue to monitor its inception from now and beyond.

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