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DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups

Comments(0)Filed under: analog, mixed-signal, mixed signal, verification, functional verification, mixed-signal verification, coverage, DVCon, functional coverage, floating point, real number, real number types, covergroups, SystemVerilogOn the last day of February 2012, I presented a proposal at the DVCon 2012 Conference to extend SystemVerilog  to support a real data type in coverpoint objects in order to facilitate mixed-signal verification for functional coverage. The paper, titled “Bringing Continuous Domain into SystemVerilog Covergroups,” reflected a year-long effort between Cadence R&D and Scott Little of Freescale (Scott moved to Intel just before we submitted our work to DVCon) that culminated in a prototype of SystemVerilog real coverage in action. We wanted to share this development with the digital verification community that usually represents the majority of DVCon crowd.


After providing a brief refresher on functional coverage basics, the paper went on to ask: “How do analog effects get captured in functional coverage while performing system level verification?” Since analog effects are described in form of floating point numbers, it becomes apparent that to meet the needs of mixed-signal in functional coverage, the language needs to support a floating point (aka real) data type. Since SystemVerilog is widely used in verification, we developed our proposal around the P1800-2009 standard of SystemVerilog.


The paper then went into the detailed mechanics of real typed SystemVerilog coverpoint objects. It highlighted an important extension to the language, specifically an instance-specific covergroup option called range_precision, to divide a range of vector bins into sub-ranges. It also explained how the existing features of SystemVerilog covergroup can be modified or extended with the introduction of real data type. Finally, the paper explored some of the challenges that are still open in the areas of floating point arithmetic and issues related to overflow and underflow. It drew a conclusion stating that our next step would be to complete an analysis of the Functional Coverage Section of the P1800 SystemVerilog Language Reference Manual (P1800-2012) and then work with the SV-EC sub-committee members for standardization of our proposal.


The audience was primarily filled with users from the digital verification community, and therefore there was a lot of curiosity in hearing a presentation coming from someone more oriented to the analog and mixed-signal world. An engineer from Dialog Semiconductor expressed strong interest in our work and stated that she found immediate use of this approach in her group’s verification initiatives. There was a concern raised by one member of the audience who wondered whether we’re trying to make the language more complex. We explained that the we were only proposing extensions that fill the gap between the existing integral type support to the desired level of real data type support.


There were some very good suggestions provided as part of audience feedback, such as consideration of logarithmic ranges and also support for the real data type for transition bins.Overall it was a very enriching experience for me and my colleagues to share our work with a community of folks who are certainly showing signs of interest to extend standard verification techniques to the wonderful world of analog. If you need further information on the presentation, please do not hesitate to contact me at prabal@cadence.com.


Prabal Bhattacharya


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