This is the second installment in an ongoing series of blog posts that includes an email conversation between Fred and Harry, two fictional mixed-signal engineers, about analog behiavoral modeling. You can read the first installment by clicking here. (NOTE: This blog post was written by Walter Hartong and uploaded by Paul Foster).
As I said, this was really the fun stuff. We are coming into the region of 1000x, 10000x or more speedup over SPICE -- that is what I was looking for. Before I tell you about the detail, it is for sure that this speedup does not come free (you know that I never trust someone who tells me that stuff comes free). We have to leave behind some of the analog behavior details, but that is fine.
OK, back to the beginning: Wreal is doing the magic. As you know, Verilog-D is not capable of using real valued ports. This is what wreal gives you. Wreal is a "wire real" or "real wire" if you want. The fun part is that even though it is a Verilog-AMS LRM construct it only needs the digital kernel for evaluation.
Thus, we are at the digital performance level and the coding style is pretty digital-like, for example:
module vco(vin, clk);
always @(vin) begin
freq = center_freq + vco_gain*vin;
clk_delay = 1.0/(2*freq);
always #(clk_delay) clk = ~clk;
It's that simple, you just connect the "vin" to your real net and you have a
I asked the Cadence guy why this is coming up now and why people haven't used this before since wreal has been in the Verilog-AMS standard forever.
Interesting answer, he said it is two-fold. One point is that there is more demand for really high speed mixed signal models from the digital teams (they have realized they can't ignore analog anymore -- like us), and secondly, Cadence has implemented some enhancements over the standard that were essential to write good models.
I will get you the details soon.
Stay tuned, Fred