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Bringing Static Analysis Methods to Mixed Signal Designs

Comments(1)Filed under: analog, mixed-signal, SPICE, OpenAccess, mixed signal design, STA, liberty model, timing model, FTM, .lib, signal integrity, static analysis, full timing model, static timing analysis

Accurate static analysis and complete coverage of the functional space remain very challenging for mixed-signal designs.  The functional verification of mixed -signal designs has never been completely possible.

It is very common to use behavioral models of analog/mixed-signal blocks during the full chip functional verification stage, and to use .lib timing models during the physical implementation stage. There are multiple issues and challenges with this approach:

  • Creating a .lib timing model of a complex analog/mixed-signal block is sometimes very difficult or impossible due to the complexity of the block.
  • Using approximate/estimated numbers in a quick timing model leads to a lot of guard-banding, and acts as a hindrance in achieving the most optimized design.
  • Having multiple views of the analog/mixed-signal block (such as design specification, behavioral model, .lib model, design schematic, physical layout, physical abstract view, etc.) might lead to erroneous designs, because all the different views are never verified against each other.

To create a more accurate .lib timing model of a complex analog/mixed-signal block, the Encounter Digital Implementation system can generate a Full Timing Model (FTM). These models enable a more accurate static timing analysis (STA) of timing paths that cross analog and digital boundaries.

An FTM  contains the complete netlist and the parasitics of the analog/mixed-signal block, which helps the designer get a "glass box" view of the block. This not only breaks the complexity of creating the .lib timing model for complex analog/mixed-signal blocks, but also opens the door to using STA methods for verifying the design.

Full Timing Model (FTM) of complex analog/mixed-signal block

The creation of FTM models becomes much easier in an OpenAccess-based physical implementation environment, where full custom analog design is visible in the digital implementation space and vice versa. The connectivity-driven layout implementation flow in Virtuoso, and the capability to understand and visualize complete design in the Encounter Digital Implementation System, enables the designers to use STA on a complete chip with a full view of signals crossing the analog and digital boundaries.

Due to the abstracted single-level view of the physical design in the digital implementation environment, designers can overcome the capacity limitation imposed by the full custom environment and make use of many other statistical and static analysis tools which are far faster than SPICE or mixed-SPICE time domain simulations.

For example, one of the most useful capabilities of the digital environment is signal integrity (SI) analysis, which uses the worst case "all aggressors" method where all the nets in the design are analyzed one by one, while assuming that the rest of all the nets in the design are aggressors. Aggressors are eliminated based on the coupling capacitance that each of them have with the victim net. This method of SI analysis is very useful for analyzing top chip-level nets in the design, including long nets that sometimes run from one corner of the chip to the other, such as busses. SI also helps analyze the transition time and signal delays on long nets.

Rajendra Pratap



By Sanjaya Sahu on August 29, 2011
Both the problem statement and the proposed solution are nicely explained..

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