Manufacturability Signoff - All Comments

There is an Applicat ...

Anonymous — Fri, 12 Mar 2010 21:26:39 GMT

There is an Application Note available on COS explaining Assura ERC flow.

We have a linkedin g ...

Anonymous — Mon, 21 Sep 2009 19:50:29 GMT

We have a linkedin group on semiconductor DFM, where you can find most of the industry leaders and university researchers.

For those who would like to explore more please join at www.linkedin.com/groups

Thanks for pointing ...

skmurphy — Wed, 22 Jul 2009 03:57:44 GMT

Thanks for pointing out "Alan Moore's Law" it was very good. There is in fact a relationship between the two laws (from Howard Landman and David Patterson)

Productivity begets quality. Automated checking begets quality.

Patterson’s Precept: Inexperience coupled with ambition leads to very large designs.

Landman’s Law: In any sufficiently large design, if there is a type of error for which you have no automatic way of checking, then the final design will contain at least one error of that type.

Landman’s Lemma: All designs are now sufficiently large. See Patterson’s Precept.

Kevin Kelly recently wrote "Was Moore's Law Inevitable?" ( www.kk.org/.../was_moores_law.php ) a long essay about Moore's Law and a family of companion curves for magnetic medium, broadcast media bandwidth etc.. that "demonstrate the effects of scaling down, or working with the small. In this microcosmic realm energy is not very important. We don't see exponential improvement in efforts to scale up."

I think you are missing out not at least reading the Watchmen graphic novel (all 12 issues of the comic book series gathered into a single volume). It's very well done and extremely thought provoking, it's not a traditional (superhero) comic at all.

TSMC has a DDK (DFM ...

wilbur — Mon, 20 Jul 2009 17:28:30 GMT

TSMC has a DDK (DFM Data Kit) for each of their process nodes that their customers can download. This kit includes models, etc... including what you asked about (defect densities that qualified CAA tools use to calculate random defect yield)

So essentially, you need the kit + a qualified CAA analysis engine/tool + your layout... and you should be good to go. Besides doing just the CAA analysis, note that some implementation tools (like Encounter) have a CAA engine available and can also read the TSMC DDK

Does TSMC and/or oth ...

Anonymous — Mon, 20 Jul 2009 05:25:48 GMT

Does TSMC and/or others produce failure rates (parts per billion) for their library models? In order to perform yield optimization (along with area, timing, and leakage) through the place and route flow?

Im interested in proactive yield optimization rather than reactive (late flow) methods such as CAA.

Please tell me what ...

Anonymous — Sun, 03 May 2009 21:43:00 GMT

Please tell me what happened to PVS/

Axel

The other thing to c ...

wilbur — Thu, 16 Apr 2009 17:54:25 GMT

The other thing to consider is separating random vs. systematic variation. If one can control systematic (through accurate modeling of the manufacturing process and application of the model to the simulation), and then add some margin for the random... that would reduce the over-margining.

There have been a burst of papers at various conferences (like SPIE) addressing variability. Since it wouldn't be proper to post the paper, drop me a note and I'll point you to it. One of the interesting findings is that at 65nm litho variation dominated and now at <=45nm context-dependent stress is dominating

Yes, I am concerned. ...

kosimov — Thu, 16 Apr 2009 02:09:47 GMT

Yes, I am concerned. 5% variation in the critical path is a target I could use, but of course would want to be able to go above and below that a reasonable amount, say, +- 5%, so, from zero to 10% for the total variation range, or, +-5% if considering direction of variations. (rough numbers; if there are reasons why similar numbers would be easier to implement, etc., of course that would be OK if in the ballpark...). I have not had experience with variation aware methodologies yet but have "wished" for them for years, at least, for a technique which was common to all design tools (at the minimum, common to the tools in a manufacturer's tool set(s)) and relatively simple and easy to use, and of course, any other blue sky spec I could think of! Seriously, though, I hope it would be easier than running multiple monte carlo analyses on old spice versions!

When you cannot get ...

Anonymous — Thu, 29 Jan 2009 19:03:36 GMT

When you cannot get closure between what you design and what you actually build with that design - sizing, placement, materials properties - you expect massive systematic failures. Design rule compliance can no longer be taken for granted. Our design and manufacture have gone beyond design verification infrastructure required for predictable execution. Yield learning is a terrible way to start learning DR violations. Extensive CD-SEM based metrology in layouts on production wafers is the right thing to do, as long as you get relevant and accurate data on DR compliance. Yet, I would think that much more is needed to regain closure.

Good points but the ...

Anonymous — Mon, 17 Nov 2008 22:57:04 GMT

Good points but the data size of scan patterns is huge.