Tidbits From TSMC Q209 Earnings Call - 40nm Yield
By Wilbur Luo
on August 7, 2009
Earning calls sure are interesting! Below is an excerpt from the TSMC Q209 call (transcript from seekingalpha). The discussion revolves around the 40nm yield issues and TSMC's ramp to improving the yield. Dr. Liu really hits on a key element of DFM...
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Filed under: Litho-aware design, CMP-aware design , Physical verification, Chip Optimization, Design for yield, Manufacturability sign-off , Manfuacturability Signoff
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Moore no More
By Christopher Clee
on April 10, 2009
"The number of watchmen required to watch the watchmen watching the watchmen tends to double every 18 months". This gem is Alan Moore's law, posted years ago by some wag in response to an Intel article on geek.com . This has, of course,...
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Filed under: EDA, Moore's law, manufacturability signoff, intel, mixed-signal, advanced node
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Assura Foundry Support
By Christopher Clee
on March 23, 2009
I've been blogging a lot about Assura recently, so I thought I would continue by talking about rule decks. Inside Cadence, we maintain a database that shows which foundries support which process for which products. This means that we can quickly give...
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Filed under: Physical verification, foundry, Assura, manufacturability signoff, system design and verification
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Assura On Steroids
By Christopher Clee
on March 17, 2009
In a recent post , I hinted at a significant performance improvement in Assura . Our R&D team focused on performance improvements in the 3.2 release, which was shipped last August. Based on our suite of performance benchmarks, we achieved an overall...
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Filed under: Manufacturability sign-off , Assura, ERC
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ERC in Assura II
By Christopher Clee
on March 10, 2009
In my last post I talked about the layout, schematic and netlist ERC capabilities of Assura. "But", I hear you ask, "is it programmable?" One of the characteristics that makes Assura such a natural fit within the Virtuoso custom design...
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Filed under: Manufacturability sign-off , Assura, ERC, SKILL
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The Buzz Around New Business Models
By Wilbur Luo
on March 6, 2009
The buzz about showing and paying for value in EDA has been building over the past few years. People have complained about the high cost of tools and EDA vendors have complained about not getting enough value from the technology that can then be re-invested...
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Filed under: CMP-aware design , Chip Optimization, Design for yield, Manufacturability sign-off , strategy for design-for-yield, foundry, Cadence Design Network, manufacturing sign off, EDA
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ERC in Assura
By Christopher Clee
on March 5, 2009
A few customers have recently asked whether we can provide schematic-based ERC checks. This is no doubt spurred by a recent product announcement by one of our competitors. No - I'm not going to say who, and I'm not going to provide a link to their...
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Filed under: Manufacturability sign-off , Assura, ERC
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Big Bang
By Christopher Clee
on March 2, 2009
When something big and expensive fails, we usually hear about it in the headlines. Recent examples include the launch failure of the Orbiting Carbon Observatory and the setback at CERN , apparently caused by a dry solder joint, that resulted in a 12-month...
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Filed under: Manufacturability sign-off , higg particle, orbiting carbon observatory
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All For One
By Christopher Clee
on February 23, 2009
Finally, sanity. Concerned about the level of electronic waste created by discarded phone chargers, the European Commission has told mobile phone manufacturers that they must adopt a standard . This will hopefully have the additional advantage of reducing...
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Filed under: Manufacturability sign-off , EDA
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Coffee, Anyone?
By Christopher Clee
on January 13, 2009
How little the world changes. Back in the days of 68000-based workstations, we would open up a design and retreat to the break room for a coffee while it loaded. Now, in the gigabyte / multicore era, we open up a design and retreat to the break room for...
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Filed under: Manufacturability sign-off , quickview
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