Home > Community > Blogs > Manufacturability Signoff > getting good silicon with more accurate timing
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Manufacturability Signoff blog (individual posts).
 

Share
  • Email
  • Social Web
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Getting Good Silicon With More Accurate Timing

By Wilbur Luo on January 9, 2009Comments(2)Filed under: Litho-aware design, CMP-aware design , Physical verification, Chip Optimization, Silicon Diagnostics , Design for yield, Manufacturability sign-off , strategy for design-for-yield, manufacturing sign off

In these difficult economic times, achieving silicon success (functional and meeting specs) within an iteration becomes an even higher priority than before; there might not be a second chance to win that socket or hit that sales window.

To that end, there appears to be a heightened interest in variation-aware methodologies to more accurately predict the electrical characteristics due to manufacturing/process variation. CMP, Litho, and stress effects all play a role in changing the transistor and interconnect characteristics at 90nm, 65nm, and below.

Are you concerned? How much variation would start being a concern for you? 5% in the critical path? 10%? I'd like to hear the risk tradeoff people make.

 

Comments(2)

By kosimov on April 15, 2009
Yes, I am concerned. 5% variation in the critical path is a target I could use, but of course would want to be able to go above and below that a reasonable amount, say, +- 5%, so, from zero to 10% for the total variation range, or, +-5% if considering direction of variations. (rough numbers; if there are reasons why similar numbers would be easier to implement, etc., of course that would be OK if in the ballpark...). I have not had experience with variation aware methodologies yet but have "wished" for them for years, at least, for a technique which was common to all design tools (at the minimum, common to the tools in a manufacturer's tool set(s)) and relatively simple and easy to use, and of course, any other blue sky spec I could think of! Seriously, though, I hope it would be easier than running multiple monte carlo analyses on old spice versions!
By wilbur on April 16, 2009
The other thing to consider is separating random vs. systematic variation. If one can control systematic (through accurate modeling of the manufacturing process and application of the model to the simulation), and then add some margin for the random... that would reduce the over-margining.

There have been a burst of papers at various conferences (like SPIE) addressing variability. Since it wouldn't be proper to post the paper, drop me a note and I'll point you to it. One of the interesting findings is that at 65nm litho variation dominated and now at <=45nm context-dependent stress is dominating

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.