In these difficult economic times, achieving silicon success (functional and meeting specs) within an iteration becomes an even higher priority than before; there might not be a second chance to win that socket or hit that sales window.
To that end, there appears to be a heightened interest in variation-aware methodologies to more accurately predict the electrical characteristics due to manufacturing/process variation. CMP, Litho, and stress effects all play a role in changing the transistor and interconnect characteristics at 90nm, 65nm, and below.
Are you concerned? How much variation would start being a concern for you? 5% in the critical path? 10%? I'd like to hear the risk tradeoff people make.