Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Manufacturability Signoff blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

What works best?

Comments(0)Filed under: Silicon Diagnostics , Silicon Signoff and Verification

Today's conventional wisdom tells us EDA folks the majority of yield loss at semiconductor companies is due to systematic issues, that's what my customers say to me. When I speak with new prospective users of my yield ramp solution, I normally see concurring facial expressions when I mention this as the most pressing problem facing product engineers.

Given this apparent reality, the majority of manufacturing failures are being caused by defects due to a specific layout being implemented using narrow process windows.  For example, lithography windows have shrunk significantly, the usable depth of focus can be ~200nm or less.  If this is the case, and we see misprints that impact a device's implementation how can we best find the topologies that are being effected the most often?

I am very curious if readers believe that traditional inspection and or metrology methods are sufficient or do we need to use diagnostic tools to correlate ATE failures to likely offending pattern in the layout?


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.