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DFM in Disguise

Comments(2)Filed under: Litho-aware design, CMP-aware design , Physical verification, Chip Optimization, Design Diagnostics, Design for yield, Silicon Signoff and Verification

DFM is an overloaded acronym/word. In some design flows, DFM can be found front-and-center and in others, it is just along-for-the-ride. It may be disguised as more rules in a process/rules design manual, or it can be quite explicit in a model-based analysis and optimization flow.

But wait, let's get through some of the formalities... My name is Wilbur and I'm an engineering manager in the front-end DFM space. My focus areas are: interconnect synthesis and optimization, model-based analysis, and pattern analysis.

I'm looking forward to sharing my thoughts and hearing yours about how we're going to add predictability and increase manufacturability in the design process. I also want to collectively ponder how the DFM space will evolve. Stay tuned...

 

 

Comments(2)

By Dennis on July 19, 2009
Does TSMC and/or others produce failure rates (parts per billion) for their library models? In order to perform yield optimization (along with area, timing, and leakage) through the place and route flow?
Im interested in proactive yield optimization rather than reactive (late flow) methods such as CAA.

By wilbur on July 20, 2009
TSMC has a DDK (DFM Data Kit) for each of their process nodes that their customers can download.  This kit includes models, etc... including what you asked about (defect densities that qualified CAA tools use to calculate random defect yield)
So essentially, you need the kit + a qualified CAA analysis engine/tool + your layout... and you should be good to go.  Besides doing just the CAA analysis, note that some implementation tools (like Encounter) have a CAA engine available and can also read the TSMC DDK

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