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Mixed-signal and Low-power Demo -- Cadence Booth at DAC

Comments(0)Filed under: low-power, low power, Palladium, mixed signal, Encounter, DAC, Design Automation Conference, low-power design, Low Power Mixed Signal Verification, ARM, Mixed Signal Verification, Virtuoso, mixed-signal low-power, microcontrollers, internet of things, Incisive, microcontroller, GLOBALFOUNDRIES, IBM

DAC is right around the corner! On the demo floor at Cadence® Booth #2214, we will demonstrate how to use the Cadence mixed-signal and low-power solution to design, verify, and implement a microcontroller-based mixed-signal design. The demo design architecture is very similar to practical designs of many applications like power management ICs, automotive controllers, and the Internet of Things (IoT). Cadene tools demonstrated in this design include Virtuoso® Schematic Editor, Virtuoso Analog Design Environment, Virtuoso AMS Designer, Virtuoso Schematic Model Generator, Virtuoso Power Intent Assistant, Incisive® Enterprise Simulator with DMS option, Virtuoso Digital Implementation, Virtuoso Layout Suite, Encounter® RTL Compiler, Encounter Test, and Conformal Low Power. An extended version of this demo will also be shown at the ARM® Connected Community Pavilion Booth #921.

For additional highlights on Cadence mixed-signal and low-power solutions, stop by our booth for:

  • The popular book, Mixed-signal Methodology Guide, which will be on sale during DAC week!
  • A sneak preview of the eBook version of the Mixed-signal Methodology Guide
  • Customer presentations at the Cadence DAC Theater
    • 9am, Tuesday, June 4  ARM  Low-Power Verification of A15 Hard Macro Using CLP 
    • 10:30am, Tuesday, June 4  Silicon Labs  Power Mode Verification in Mixed-Signal Chip
    • 12:00pm, Tuesday, June 4  IBM  An Interoperable Flow with Unified OA and QRC Technology Files
    • 9am, Wednesday, June 5  Marvell  Low-Power Verification Using CLP
    • 4pm, Wednesday, June 5  Texas Instruments  An Inter-Operable Flow with Unified OA and QRC Technology Files
  • Partner presentations at the Cadence DAC Theater
    • 10am, Monday, June 3  X-Fab  Rapid Adoption of Advanced Cadence Design Flows Using X-FAB's AMS Reference Kit
    • 3:30pm, Monday, June 3  TSMC TSMC Custom Reference Flow for 20nm -  Cadence Track
    • 9:30am,Tuesday, June 4  TowerJazz   Substrate Noise Isolation Extraction/Model Using Cadence Analog Flow
    • 12:30pm, Wednesday, June 5  GLOBALFOUNDRIES  20nm/14nm Analog/Mixed-signal Flow
    • 2:30pm, Wednesday, June 5  ARM  Cortex®-M0 and Cortex-M0+: Tiny, Easy, and Energy-efficient Processors for Mixed-signal Applications
  • Technology sessions at suites
    • 10am, Monday, June 3    Low-power Verification of Mixed-signal Designs
    • 2pm, Monday, June 3      Advanced Implementation Techniques for Mixed-signal Designs
    • 2pm, Monday, June 3      LP Simulation: Are You Really Done?
    • 4pm, Monday, June 3      Power Format Update: Latest on CPF and IEEE 1801  
    • 11am, Wednesday, June 5   Mixed-signal Verification
    • 11am, Wednesday, June 5   LP Simulation: Are You Really Done?
    • 4pm, Wednesday, June 5   Successful RTL-to-GDSII Low-Power Design (FULL)
    • 5pm, Wednesday, June 5   Custom/AMS Design at Advanced Nodes

We will also have three presentations at the Si2 booth (#1427):

  • 10:30am, Monday, June 3   An Interoperable Implementation Solution for Mixed-signal Design
  • 11:30am, Tuesday, June 4   Low-power Verification for Mixed-signal Designs Using CPF
  • 10:30am, Wednesday, June 5   System-level Low-power Verification Using Palladium


We have a great program at DAC. Click the link for complete Cadence DAC Theater and Technology Sessions. Look forward to seeing you at DAC!     


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