All engineers can enhance their mixed-signal low-power structural verification productivity by learning while doing with a PIEA RAK (Power Intent Export Assistant Rapid Adoption Kit). They can verify the mixed-signal chip by a generating macromodel for their analog block automatically, and run it through Conformal Low Power (CLP) to perform a low power structural check.
The power structure integrity of a mixed-signal, low-power block is verified via Conformal Low Power integrated into the Virtuoso Schematic Editor Power Intent Export Assistant (VSE-PIEA). Here is the flow.
Applying the flow iteratively from lower to higher levels can verify the power structure.
Cadence customers can learn more in a Rapid Adoption Kit (RAK) titled IC 6.1.5 Virtuoso Schematic Editor XL PIEA, Conformal Low Power: Mixed-Signal Low Power Structural Verification.
The RAK includes Rapid Adoption Kit with demo design (instructions are provided on how to setup the user environment). It Introduces the Power Intent Export Assistant (PIEA) feature that has been implemented in the Virtuoso IC615 release. The power intent extracted is then verified by calling Conformal Low Power (CLP) inside the Virtuoso environment.
- Last Update: 11/15/2012.
- Validated with IC 6.1.5 and CLP 11.1
The RAK uses a sample test case to go through PIEA + CLP flow as follows:
- Setup for PIEA
- Perform power intent extraction
- CPF Import: It is recommended to Import macro CPF, as oppose to designing CPF for sub-blocks. If you choose to import design CPF files please make sure the design CPF file has power domain information for all the top level boundary ports
- Generate macro CPF and design CPF
- Perform low power verification by running CLP
It is also recommended to go through older RAKs as prerequisites.
- Conformal Low Power, RTL Compiler and Incisive: Low Power Verification for Beginners
- Conformal Low Power: CPF Macro Models
- Conformal Low Power and RTL Compiler: Low Power Verification for Advanced Users
To access all these RAKs, visit our RAK Home Page to access Synthesis, Test and Verification flow
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