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Low-Power Technology Summit Proceedings Now Available

Comments(0)Filed under: Hardee, PSO, shutoff, MSV, DVFS, Dynamic power, mixed-signal, mixed signal, MVt, power shutoff, power gating, power shut-off, low-power design, Luke Lang, Qi Wang, Substrate bias, body bias, reverse bias, freescale, kinetis, multi-bit flops, power optimization, back bias, ground level shifter, Low Power Mixed Signal Verification, Anis Jarrar, POP, ARM, Broadcom, physical IP, low power summit, Jan Rabaey, Berkeley Wireless Research Center, BWRC, power domains

On October 18, 2012 Cadence held a Low-Power Technology Summit at our San Jose, California headquarters. Experts from Cadence and other leading companies presented the latest low-power design methodologies. Well, it took us a while but you can now view the material via the Low-Power Technology Summit Proceedings archive, which just went live.

We've put both video and PDF versions of the presentations there. Obviously the PDFs give you the quickest access to the material, but you'd be missing a lot to just grab those. Seeing and hearing the presenter in action is important, especially when one of the keynotes, entitled "The power wall - are we scaling it or is it just getting higher?", is delivered by a noted expert like Professor Jan Rabaey of the University of California at Berkeley. The videos also have the Q&A sessions at the end of each presentation -- there were lots of good questions, and good interaction. You do need a "Cadence Community" login to access those, so there will be a quick one-time registration for the login if you don't already have it.

Prof. Jan Rabaey presents at the Low Power Technology Summit 

As well as the keynote from Professor Rabaey (which Richard Goering also covered in a blog here), there were also presentations from Sathya Subramanian of ARM on Low-Power Design with ARM® Physical IP and POPTM IP, and technical updates from the Cadence team.

My personal highlight from the day was the presentation by Anis Jarrar of Freescale. Anis talked about all the measures they took to meet the aggressive power specifications on the Kinetis family of chips. Kinetis has been highly successful for Freescale, and they really are using all the tricks in the book (and then a few that aren't) to minimize power on these designs. You can also find more about Kinetis here. As well as the usual techniques (clock-gating, multi-Vt, Multi-Supply Voltage, Power Shut-off) they were also an early user of multi-bit register mapping in RTL Compiler. Further, they found a novel way to apply body bias that avoided the need for that inefficient, tricky way to generate a negative bias supply -- the charge pump. The audience was very happy to learn more about Anis's experiences, and the Q&A session for this one was lively and informative.

Finally, the presenters were joined by representatives of Broadcom and Berkeley Wireless Research Center for a panel session moderated by Richard Goering. Panelists provided a great low-power design-related discussion. You can also read Richard's blog on that, for a summary.


Pete Hardee


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