The recent Low-Power Technology Summit held at Cadence headquarters in San Jose gave us a great opportunity to take the pulse of low-power design by surveying the attendees. Some of the data we got was expected, but there were a couple of surprises.
First, some of the expected stuff. We'd noticed in the last major surveys done almost two years ago (see the Perspective on Power blog from December 2010) that advanced low-power design techniques were starting to be applied outside of mobile (battery-operated) devices, and this trend has increased. 49% of the attendees surveyed worked on non-mobile end-applications. As in 2010, very nearly 100% were already using basic low-power techniques like clock gating and multi-Vt optimization. But the people using advanced techniques "currently" increased from 60% to 70% (see figure below).
As before, we define advanced low power techniques as the ones that apply to power domains - splitting the design into separately-powered areas where the voltage can be shut off to reduce leakage (Power Shut-Off - PSO, aka State Retention Power Gating - SRPG) or supplied with different voltage levels (permanently in the case of Multi-Supply Voltage - MSV, or dynamically in the case of Dynamic Voltage and Frequency Scaling - DVFS).
As in 2010, PSO was the most popular of the advanced techniques, followed by MSV, then DVFS. What was less expected was that, in contrast to 2010 where the "future" use of advanced techniques increased all of them proportionately, in the 2012 results, the designers surveyed were expecting to use a lot more DVFS in their next designs, pushing it into second place in front of MSV.
So why might DVFS become more popular than MSV? Both use different supply voltages for domains that have different performance needs. The difference is that DVFS allows the voltage level, or more usually a combination of voltage and clock speed, to be selected on the fly based on current performance demand. It is therefore a more complex technique to implement and verify, meaning that the designer has to achieve sign-off for power domain to which it applies at multiple modes and corners.
Also, opportunities to apply MSV may have already been fully exploited and designers are looking for more. Recently, design tools such as the Cadence Encounter RTL-to-GDSII flow support design closure for multi-mode multi-corner (MMMC) simulations, which is an important enabler for an increase in the use of DVFS on the next generation of designs.