It looks like it might be standing room only for latecomers to the Low-Power Technology Summit at Cadence headquarters building 10 auditorium this Thursday (18 October). Registration has been very strong. I'm expecting a great day -- we have a full agenda covering multiple aspects of low-power design.
No longer the sole preserve of designers needing to extend battery life, low-power design has become ubiquitous in many different applications from mobile devices to datacenters. We have recently seen a bifurcation in the needs of our customers --- on the one hand, for power optimization in high-performance digital design, and on the other hand, ultra-low-power design techniques in a myriad of smaller, lower performance but none-the-less challenging mixed-signal devices. There will be technology updates from Cadence focusing in each of these areas. We also expect the audience to be given plenty to think about from our keynote speaker, Professor Jan Rabaey, of U.C. Berkeley. I just wanted to highlight a few of my favorites that I'm really looking forward to from the agenda.
- Keynote speech by Professor Jan Rabaey - see Richard Goering's blog from a couple of weeks ago for more information on Professor Rabaey
- Sathya Subramanian of ARM will talk about low-power support in ARM's physical libraries, memories, and also optimization of processor implementation with POPTM IP and ARM-Cadence collaboration on design flows
- Anis Jarrar of Freescale will talk about low-power design experiences on the latest Kinetis series of ARM Cortex®M-powered mixed-signal chips
- Panel discussion moderated by Richard Goering with interesting diverse and experienced panelists:
Sathya Subramanian of ARM
Qi Wang of Cadence
Anis Jarrar of Freescale
Sushma Honnavara-Prasad of Broadcom
Gary Kelson of the Berkeley Wireless Research Center
For more details on the agenda, times and logistics, please see the Cadence event page.
See you on Thursday!