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Your First Low-power Verification Project - Webinar

Comments(0)Filed under: low-power, PSO, UPF, CPF, IES, power shutoff, IEEE 1801, Functional Verification, webinar

So your team just specified its first design with power management circuits.  The designers are telling you, its just a few power shut-off domains defined by CPF or UPF.  The verification should be easy-peasy right?  Wrong.  Each domain has complete controls, isolation, and retention.  As a verification engineer, you know that any test could trigger a power change either intentionally or in error.  How do you build your environment to verify this first low-power project?

Mickey Rodriguez, Cadence low-power verification product engineer has answers for you.  In a webinar on Tuesday October 16 at 9:00 am PDT, Mickey will lead a technical discussion entitled "5 Steps to Your First Power Shutoff (PSO) Verification". The discussion will cover these key topics and utilize the low-power reference implementation in the Incisive Verification Kit provided within with the Incisive Enterprise Simulator:

  • Explaining PSO concepts including isolation and retention
  • Checking the power format file for errors using low-power rules in Incisive HAL
  • Understanding and debugging corruption in Verilog
  • Identifying typical PSO bugs using SimVsion low-power debug
  • Leveraging assertions to increase quality and generate low-power verification coverage

So if you are a digital IP designer intersted in knowing how your PSO circuit will be verified, a verification engineer responsible for that verification, or a project manager trying to balance project risk and tighten power-budget requirements, this webinar is for you!

You can sign-up for the webinar here:  http://www.cadence.com/cadence/events/Pages/eventseries.aspx?series=Functional%20Verification%20Webinar%20Series%202012&CMP=Home

 =Adam "The Jouler" Sherer, Incisive Product Marketing Director 


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