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Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year

Comments(0)Filed under: low-power, low power, MSV, CPF, power analysis, Palladium, MVt, Common Power Format, Encounter, power shut-off, 28nm, low-power design, Sorin Dobre, Qualcomm, advanced verification, CDNLive, CDNLive!, freescale, kinetis, CDN Live, Conformal Low Power, Low Power Mixed Signal Verification, CPF Macro Modelling, Anis Jarrar

CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We're three-quarters the way through the events at the time of writing -- you can see the whole program on www.cadence.com at the CDNLive! 2012 Worldwide page. Proceedings are published so far from San Jose, USA; Munich, Germany; and Hsinchu, Taiwan. If you click on those proceedings links, you get to a multitude of different tracks and, for those interested in everything low-power, it can be quite challenging to find all the relevant presentations. So I've saved you the trouble of hunting through by gathering them all here - 12 so far from Cadence customers plus 3 useful presentations from Cadence's own technologists.

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A Comprehensive Approach to Verifying Low Power Mixed Signal Design using Conformal LP  
Norman Chan, Rambus

Conformal Low Power - Complex Low Power Design Verification                                               
Sorin Dobre, Qualcomm

CPF in AMS Simulation and Macro IP                                                                                     
Qingyu Lin, Cadence

Low Power Implementation on Freescale Kinetis Family                                                           
Anis Jarrar, Freescale Semiconductor

Techtorial: Low Power Failures--What not to Plan                                                                     
John Decker, Cadence

Low-power Verification using UVM SystemVerilog                                                                     
John Decker, Cadence

Automation of Switch Insertion and Power Network Generation in 28nm PSO Designs                 
Shane Stelmach et al, Texas Instruments

Multi Voltage Domain, Multi VT Low power physical implementation with Cadence tool suite         
Harald Hopperdietzel & Uwe Ratzmann, Texas Instruments

Power Calculation From Early Estimation to Silicon Correlation                                                 
Johannes Bruecker, Renesas Electronics

Implementation of a Flexible, Low Power and High Performance 4G Baseband Processor             
Peter Debacker et al, imec

Hierarchical CPF Usage in ST-HED Low Power Flow                                                                 
Sylvie Pierunek, STMicroelectronics

Early, Functional Unit-Based, Power Estimation for Wireless Baseband Processors                     
Peter Debacker et al, imec

Challenging Verification for Complex Low-Power Design without Always-Power-On Domain           
Zhaohui Hu, ST-Ericsson

Effective GPU platform verification and power estimation solutions with Palladium                         
Kaowen Liu, MediaTek

Design Closure in 28nm Low-Power Design with EDI                                                                 
Jurcy Huang, Socle

Huge thanks to all who contributed these presentations!

Pete Hardee


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