Why do you define macro models? Luke Lang, Engineering Director at Cadence, says that "Just because you have a hard macro doesn't mean you need to define a macro model: A single-domain hard macro without any low power component should be black-boxed. A macro model is not necessary."
Luke further elaborates: "Custom IP blocks and analog macros often contain low-power features. A pure black box makes verification and implementation almost impossible. So, you need macro modeling as it provides the necessary power information to enable verification and implementation." The diagram below depicts Common Power Format (CPF) macro models.
Embedded RAM with always-on memory core but with power shutoff (PSO) interfaces.
Analog macro that turns off a portion of the circuit.
Embedded processor that operates with dynamic voltage and frequency scaling (DVFS).
Cadence customers can learn more in a Rapid Adoption Kit (RAK) titled Conformal Low Power and RTL Compiler: Low Power Verification for Advanced Users. The kit includes overviews, tutorials with demo design (instructions are provided on how to set up uthe ser environment) and provides introductions for the advanced features of Conformal Low Power -- including Power Intent Comparison, Hierarchical Integration and CPF Macro Modeling.
You can also find a low power (LP) Mixed Verification presentation that talks about:
Overview of LP structural verification
Application of LP structural verification to mixed-signal designs
Generation of CPF macro model
While providing an overview on hierarchical flow and integration, the Cadence Low Power team also shares some confidential tips and techniques on Macro Cell Modelling. There are several "learning-by-doing" labs to cover these advanced features of the Conformal Low Power verification solution. They will surely make you productive and proficient with Cadence tools and technologies.
To download this Advanced CLP RAK, click here. To access all RAKs, visit our RAK Home Page
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