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Mixed Signals from European Low-Power Designers

Comments(0)Filed under: low-power, low power, MSV, DVFS, Dynamic power, wreal, mixed-signal, mixed signal, Common Power Format, power shutoff, power gating, reliability, Moore's Law, Europe, European designers

Early summer is a good time to visit Europe.  I was there for the first couple of weeks in July, before most of Europe disappears on vacation. I spent my time mainly with customers in Germany, Ireland and the UK. It's not the weather that makes it a good time to visit - while it was nice in Germany the Northern European summer has been a disappointment so far, although the two days I spent in Scotland were, I'm told, the first two rain-free days since April.

It was a good time because our customers were keen to get a mid-year update, especially since so few make the trip over to DAC nowadays. And we had plenty of interesting stuff to share. But the value for me is not really the communication of our latest stuff to our customers; it's more listening to what their changing needs are. More than I'd ever experienced before, the needs stem from the confluence of low-power and mixed-signal design challenges.

While much of the semiconductor industry globally seems preoccupied with digital design in advanced nodes like 28nm, and starting to think about 20nm and beyond, you can practically count the companies in Europe involved with such designs on the fingers of one hand. However, if I try to count the companies involved with mixed-signal designs, combined with the need to meet stringent power specifications, I fast run out of digits.

The European chip design scene is all about mixed-signal and low-power in a wide range of mobile, automotive, industrial and medical applications. While designs tend to be implemented in less advanced process nodes - in companies I visited many new designs are moving to the 65nm node and designs at 90nm, 130nm and even 180nm are still commonplace - the designs are every bit as challenging. The challenges are just different. In the pure digital world, unless you've been living under a rock for the past couple of decades, you probably know that CMOS process technology has been able to follow Moore's Law - the approximate doubling of transistor count every two years. Try doing that with RF devices, passives, power management components, MEMS, or in short, all of those components you need to interface with the (analog) real world. Fabs specializing in mixed-signal technologies have recently coined the phrase "More than Moore" to describe this challenge.

Power-wise, these mixed-signal designs are no less challenging. Medical devices and smart card applications in particular have pushed back the state-of-the-art in ultra-low-power design. Power specifications in the automotive world have become tighter and tighter as the rapidly-growing electronics content adds up to significant power demand, and power densities are strictly controlled to avoid temperature-related reliability issues in an already pretty hostile environment.

Depending on the application, and given the process nodes in use, most emphasis so far has been on reduction of dynamic power. Aggressive techniques including multi-supply voltages, and dynamic voltage and frequency scaling are commonplace. But with the move to 65nm and beyond, and especially if the application involves extended idle periods, controlling leakage is becoming more important and power gating is starting to be more widely deployed. While the complexity of power architectures may not seem to be as great as the latest mobile multimedia platform, nonetheless it's introducing multiple power domains and multiple power modes on top of the existing complexities of mixed signal design.

This is critical, especially since verification complexity increases exponentially with complexity of the power architecture, and mixed-signal verification is already considerably more challenging than digital verification. Why? Continuous waveforms simulate slower than discrete, and techniques from the digital world like formal verification and hardware acceleration are almost impossible to apply, if the conventional mixed-signal verification methodology continues.

So, many customers were interested in recent developments at Cadence that bring our mixed-signal and low-power solutions closer together. This inlcudes capabilities like power-aware mixed signal simulation with real number modeling (i.e. wreal). Here, signals crossing the analog and digital domains are not just modeled abstractly for speed, but electrical-to-logical and logical-to-electrical conversion is power-aware, meaning all the logic states and their equivalent voltages are derived automatically from the Common Power Format (CPF) file. Also important is the ability to generate CPF from the analog circuitry in the Virtuoso schematic view, which makes a block that would be functionally a "black box" in digital formal verification tools like Conformal Low Power, look like a "white box" from the power intent point of view, enabling rigorous chip-level functional and structural checks of the integrated design's power intent. Mixed-signal and low-power design challenges seem daunting enough individually, but we're really starting to see what happens when they coincide. And hopefully, we're doing something useful about it.

Pete Hardee 


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