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What’s Cool for Low-Power at DAC?

Comments(0)Filed under: low-power, power, low power, PSO, UPF, power-aware, CPF, power analysis, mixed-signal, mixed signal, CPF 2.0, Common Power Format, power shutoff, power gating, power shut-off, DAC, Design Automation Conference, low-power design

Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design, implementation and verification of this important subject, there's a lot to choose from at Cadence's booth #1930. Here is a quick guide to presentations, demos and other events Cadence is involved with for low-power, as well as the latest updates on tools and flows support.

1.       Luncheon on Overcoming the Challenges of Embedding Ultra Low-Power, ARM 32-bit Processors into Analog/Mixed-Signal Designs. Time: Tuesday June 5th. 12:00PM - 1:00PM (doors open and food is served at 11:30 AM). Location: 270-276 (Moscone Convention Center). Register here.

2.       Three exciting customer presentations on low-power design in the Cadence EDA360 Theater at Booth 1930:

o   Marvell on accelerating low-power implementation using CPF, Monday June 4th at 12:30PM

o   Maxim on designing their ADCs with the Cadence low-power/mixed signal flow, Monday June 4th at 3:00PM

o   Broadcom on a designer's perspective on power formats, Tuesday June 5th at 4:30PM

3.       A demo of applying the latest mixed-signal verification methodology on a mixed-signal design using Cortex-M0 in ultra low power application. Time: Monday June 4th - Wednesday June 6th. Location: ARM Booth #1414, #802.

4.       Cadence booth demo pods - Monday June 4th - Wednesday June 6th 9:00AM-6:00PM, at Booth #1930:

o   Low-Power Verification in Mixed-Signal Design

o   Incisive Low-Power Verification with UVM SystemVerilog and e

5.       Optimizing Power, Reducing Energy, and Meeting Schedule using an Advanced Low-Power Solution. Time: Monday Jun 4th 5:00PM-6:00PM, Tuesday June 5th 10:00AM-11:00AM, Wednesday June 6th 3:00PM-4:00PM. Location Cadence Demo Suite #2 at Booth 1930.

6.       Meeting Power Targets using a Digital Front-End Design and Verification Solution. Time: Monday June 4th 9:00AM-10:00AM, Tuesday June 5th 1:00PM-2:00PM. Location Cadence Demo Suite #3 at Booth 1930.

7.       Implementing Low-Power and High-Performance ARM® CortexTM Processor-Based SoCs. Time: Monday Jun 4th 11:00AM-1:00PM, Tuesday June 5th 2:00PM-4:00PM, Wednesday June 6th 11:00AM-1:00PM. Location Cadence Demo Suite #3 at Booth 1930.

8.       Achieving Faster Timing and Power Closure using an Advanced Digital Signoff Analysis Solution. Time: Monday June 4th 3:00PM-4:00PM, Tuesday June 5th 10:00AM-11:00AM, Wednesday June 6th 11:00AM-1:00PM. Location Cadence Demo Suite #3 at Booth 1930.

9.       Improving Verification Coverage and Reducing Silicon Re-Spins for Functional and Low-Power Verification of Mixed-Signal Designs. Time: Monday June 4th 3:00PM-4:00PM, Wednesday June 6th 4:00PM-5:00PM. Location Cadence Demo Suite #2 & #3 at Booth 1930.

Not forgetting of course the Denali Party by Cadence. See you at DAC!

Pete Hardee 

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