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Assertions Help Avoid Chip Melt

Comments(0)Filed under: low-power, AVS, simulation, IES, verification, Ann Mutschler, ABV, Assertions
When asked why the use of assertions for low power is rising, I say “at 40nm and below, the chips are just going to melt.” Ann Steffora Mutschler, you quoted me perfectly in your “Avoiding Chip Melt” article!

Assertions are just the tip of the low-power verification iceberg. (Yep:  iceberg + low-power +melting chips = metaphorical mayhem!)  Kidding aside, in the article, both Erich Marschner from Mentor and I cite the breadth of issues facing complex, multi-domain power-aware chips.  We agree that assertions are a simple starting point for designers to outline their power intentions for the verification team to verify.  In the Cadence Incisive solution, we take it a step further by generating the power assertions directly from the power-format file.

But as we said, that’s just the start.  Teams with power-aware designs should be running low-power in every regression test because any one of those tests could trigger a change in power-state and the simulator should respond appropriately. Doing so will also make it easier to verify the power-aware aspects of the verification plan.  With Incisive, you can also generate verification plans from your power-format file and collect coverage to gain a better understanding of the quality of your power-aware circuits.  To learn more about this, please attend John Decker’s upcoming “How to Avoid Low-Power Failures” webinar on April 4.

So whether you’re facing the risk of a melting 40nm chip or just trying to differentiate your product by making it power aware, consider low-power assertions as the first step toward a comprehensive low-power verification methodology.

=Adam “keep it cool” Sherer, Cadence Product Director


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